The proliferation of IoT devices in Software-Defined Data Center (SDDC) environments has made large-scale, real-time failure prediction both critical and complex. Traditional monitoring systems remain reactive, generating disconnected alerts with limited context. In this paper, we present a novel, digital twin-driven framework that unifies semantic modeling, machine learning, and real-time telemetry to deliver intelligent, predictive maintenance for IoT infrastructures. Built upon an extensible ontology derived from the Semantic Sensor Network (SSN) standard and enriched with dynamic battery metadata, our system integrates classification and regression models, such as Random Forest and XGBoost, to forecast device failures and estimate Remaining Useful Life (RUL). These insights are contextually embedded into a live semantic layer, enabling expressive SPARQL queries for impact analysis and proactive fault management. To further democratize access, we integrate a Large Language Model (LLM) interface that translates natural language queries into SPARQL, bridging the gap between technical complexity and user accessibility. Validated on NASA’s battery datasets, our approach demonstrates superior explainability, operational relevance, and scalability—pushing the boundaries of predictive analytics in IoT-SDDC ecosystems. We also showcase case studies with five practical scenarios where our framework can be readily integrated and used.

With increasing transistor density on a single chip, processor design in the nanoscale era is hitting power and frequency walls. Due to these challenges, processors not only need to run fast, but remain cool and consume less energy. At this juncture where no further improvement in clock frequency is possible, data dependent latching through timing speculation provides a silver lining. In this paper, (a) we present a novel power level switching mechanism using reliable and aggressive designs that support overclocking. Using the proposed framework, we achieve 40 percent speed-up and also observe 75 percent energy-delay squared product (ED2) savings relative to the base architecture. (b) showcase the loss of efficiency in current chip multiprocessor systems due to excess power supplied. We propose a utilization-aware task scheduling (UTS) - a power management scheme that increases energy efficiency of chip multiprocessors. (c) demonstrate that UTS along with aggressive timing speculation extracts ample performance from the system without loss of efficiency, and also without breaching power and thermal constraints. We demonstrate that UTS improves performance by 12 percent due to aggressive power level switching and over 50 percent in ED2savings in comparing to traditional power management techniques.