Blockchain technology is emerging in various fields, to guarantee security of digital currency and internet of things. In this paper, we provide incentive to encourage edge servers to serve mobile users for the mobile blockchain application. We formulate the problem as a resource allocation problem, then we propose a three-stage auction to implement resource allocation specially designed for mobile blockchain, and introduce the group-buying mechanism to motivate mobile users. We prove that our auction scheme is truthful, individual rationality, and computational efficiency. We compare proposed scheme with TACD and HAF mechanisms, and simulation results show that the social welfare achieved by our scheme is higher than that of TACD and HAF mechanisms.

Because of the subjectivity of human beings, the evaluation of image complexity in the Human Vision System (HVS) cannot be provided accurately by traditional image complexity evaluation models. In the 2016 Conference on Computer Vision and Pattern Recognition (CVPR 2016), an evaluation method of visual search difficulty based on the visual search time was proposed for the first time. In this paper, the ordinal relation of the image complexity for human perception was discussed, and a quantitative evaluation model based on Convolutional Neural Network (CNN) features and Support Vector Ordinal Regression (SVOR) with explicit inequality constraints on the thresholds was proposed. The results showed that the evaluation models based on SVOR and pyramid CNN features of images can describe the order relation of image complexity among different images more accurately, which achieve the Kendall’s tau correlation of 0.4858, better than SVR overall under the same condition, whose highest Kendall’s tau correlation is 0.4794.

This paper presents a read-out circuit for capacitive and resistive sensors with large scale which converts capacitance or resistance to frequency. It utilizes a high precision and high speed comparator to control the oscillation. A method using correlated double sampling (CDS) technique in continuous-time comparator is proposed to attenuate the DC offset and low frequency flicker noise. A calibration circuit was adopted for the on-chip resistance used for capacitive sensors to achieve small variation caused by temperature. This design is based on 0.18μm CMOS process. The circuit works well when capacitance values are in the range from 10 pF to 100 pF and resistance values are in the range from 20 KΩ to 150 KΩ. Simulation results show that the variation of oscillation frequency is only 0.2% from −40 □ to 80Ό, and the minimum capacitance and resistance could be detected is 20 fF and 40 Ω respectively. The power consumption of the read-out circuit is about 40.4 μW, which could be easily integrated in a UHF RFID tag.

This paper describes the capacitorless 1-transistor (1T) DRAMs exploits the floating body (FB) effect of Fully depleted (FD) SOI devices, where the transistor body is used as a charge storage node. A novel three-tier, 3D, 1T embedded DRAM is presented that can be vertically integrated with the microprocessor achieving low cost, high density on-chip main memory. A 394Kbits test chip is designed and fabricated in a 0.15um fully depleted SOI CMOS process. The measured retention time under holding conditions is higher than 10ms. In the continuous read mode, every read should be followed by a refresh. The test chip is designed to work with an access time of 50ns and operates at 10MHz.