Autoencoders (AEs) have attracted significant attention for hyperspectral anomaly detection (HAD) in remote sensing applications due to their ability to unveil small, unique objects scattered across large geographical regions in an unsupervised manner. However, the training and inference processes of AEs are computationally demanding, posing challenges for efficient HAD in resource-constrained onboard applications. Various optimization techniques and parallel computing approaches have been proposed to alleviate the computational burden and enhance the feasibility of AEs for real-time applications in HAD. In this paper, we first present an efficient lightweight autonomous autoencoder (LAutoAE) that addresses the computational challenges of the autonomous hyperspectral anomaly detection autoencoder (AUTO-AD) while maintaining a similar anomaly detection accuracy. To further enhance the accuracy, we introduce LAutoAE+, which integrates kernel principal component analysis (KPCA) based pre-processing methods with the LAutoAE. Experiments on diverse datasets demonstrate that the proposed LAutoAE and LAutoAE+ achieve comparable or superior detection performance compared with conventional Auto-AD, while also achieving reductions of 87% and 89.4%, respectively, in the number of learnable parameters.

Modern cyber-physical systems often make use of heterogeneous systems-on-chip with reconfigurable logic to provide adequate computing power and flexible I/O. However, modeling, verifying, and implementing the computations spanning CPUs and reconfigurable logic are still challenging. The hardware and software components are often designed by different teams and at different levels of abstraction, making it hard to reason about the resulting computation. We propose to lift both hardware and software design to the same level of abstraction by using the Lingua Franca coordination language. Lingua Franca is based on a sparse synchronous model that allows modeling concurrency and timing while keeping a sequential model for the actual computation. We define hardware reactors as a subset of the reactor model of computation underlying Lingua Franca. We also present and evaluate reactor-chisel, a hardware runtime implementing the semantics of hardware reactors, and an extension to the Lingua Franca compiler enabling reactor-oriented hardware–software codesign.

With increasingly complex workloads and the end of Dennard scaling, the need for heterogeneous computing is becoming apparent. SoC FPGAs (System-on-chip Field-Programmable Gate Arrays) are a promising solution to this need. They combine the versatility of CPU s and the reconfigurability and high performance of FPGAs. SoC FPGAs have received a great deal of attention in recent years from both academia and chipmakers. However, the task of hardware-software codesign, posed by these platforms, remains challenging. This is partly due to the lack of vendor-neutral abstractions for building and evaluating designs. Chisel is a promising hardware construction language based on the idea of writing hardware generators. In this paper, we present FPGA-tidbi ts, an open-source, vendor-neutral Chisel library for rapid prototyping of accelerators for SoC FPG As.

The assignment problem is a fundamental optimization problem and a crucial part of many systems. For example, in multiple object tracking, the assignment problem is used to associate object detections with hypothetical target tracks and solving the assignment problem is one of the most compute-intensive tasks. To enable low-latency real-time implementations, efficient solutions to the assignment problem is required. In this work, we present Sparse and Speculative (SaS) Auction, a novel implementation of the popular Auction algorithm for FPGAs. Two novel optimizations are proposed. First, the pipeline width and depth are reduced by exploiting sparsity in the input problems. Second, dependency speculation is employed to enable a fully pipelined design and increase the throughput. Speedups as high as 50 × are achieved relative to the state-of-the-art implementation for some input distributions. We evaluate the implementation both on randomly generated datasets and realistic datasets from multiple object tracking.

Sporadic ocean color events with characteristic spectra, in particular algal blooms, call for quick delivery of high-resolution remote sensing data for further analysis. Motivated by this, we present the mission design for HYPerspectral Smallsat for Ocean observation (HYPSO-1), a 6U CubeSat at 500 km orbital altitude hosting a custom-built pushbroom hyperspectral imager with wavelengths 387–801 nm at 3.33 nm bandpass and a swath width of 70 km. The imager’s expected signal-to-noise ratio is characterized for typical open ocean water-leaving radiance which can be flexibly increased by binning pixels. Using geometric principles, the satellite shall execute a slew maneuver during a scan to induce greater overlap in the pixels with a goal to enable better than 100 m spatial resolution. Since high-dimensional hyperspectral data need to be transmitted over limited space-to-ground communications, we have designed a modular FPGA-based onboard image processing architecture that significantly reduces the data size without losing important spatial-spectral information. We justify the concept with a simulated scenario where HYPSO-1 first collects numerous hyperspectral images of a 40 km by 40 km coastal area in Norway and aims to immediately transfer these to nearby ground stations. Using CCSDS123 lossless compression, it takes about one orbital revolution to obtain the complete data product when considering overhead in satellite bus communications and less than 10 min without the overhead. It is shown that even better latency can be achieved with more advanced onboard processing algorithms.

The H.264/AVC standard supports intra prediction in order to reduce spatial redundancy in the video frame. The intra prediction process for one macro block requires reconstructing the left and top neighbor macro blocks where the reconstruction path includes a number of processing units such as integer transform, quantization, inverse quantization and inverse integer transform. In order to meet the real time performance constraints of different video standards, a high throughput through this path is necessary. In this paper we propose architecture for real time implementation of the reconstruction path used in the H.264/AVC where the hardware is designed to be used as part of a complete H.264 video coding system. Each processing block executes in a single clock cycle for all calculations required for one 4×4 block. In order to minimize area cost while maintaining the performance, dynamic partial reconfiguration is employed in the quantization and inverse quantization modules such that an area - efficient solution is found without impairing the throughput.

The objective of this project is to build a platform for autonomous, on-demand systems within video processing and other digital processing algorithms that require intensive computations and where mobile clients can save energy by off-loading computations to servers in the environment. Self-reconfiguration provides a necessary degree of flexibility for such systems, and a practical run time reconfiguration tool has already been built as part of a larger project. This includes a hardware operating system which also handles persistence of modules by saving and loading their defined state variables when (de)scheduled.