This work introduces Single Instruction Multi-Thread Express (SIMT-X), a general-purpose Central Processing Unit (CPU) microarchitecture that enables Graphics Processing Units (GPUs)-style SIMT execution across multiple threads of the same program for high throughput, while retaining the latency benefits of out-of-order execution, and the programming convenience of homogeneous multi-thread processors. SIMT-X leverages the existing Single Instruction Multiple Data (SIMD) back-end to provide CPU/GPU-like processing on a single core with minimal overhead. We demonstrate that although SIMT-X invokes a restricted form of Out-of-Order (OoO), the microarchitecture successfully captures a majority of the benefits of aggressive OoO execution using at most two concurrent register mappings per architectural register, while addressing issues of partial dependencies and supporting a general-purpose Instruction Set Architecture (ISA).

Many researchers seek for alternatives to traditional computing architectures, often placing emphasis on modeling biological systems that possess intelligence and learning capabilities. Cortical columns have emerged as a high-level unsupervised learning model for extracting independent data features in a hierarchical manner. Previous cortical models simply rely on software based techniques and neglect the actual purpose of investigating these architectures: to diverge from the conventional Von Neumann approach to an actual hardware realization of an intelligent system. This work presents the hardware realization of a cortical column system, taking several factors into consideration which were previously disregarded by software models. We introduce a Neural Spike Dual-Rail communication scheme, and a temporal pooling unit capable of detecting data distortions during training and testing. This work concludes with a study on cortical columns and their hierarchical impact on hardware resources.

As SoC applications demand high performance and integration density, SoC designers consider multiple aspects during the design phase. This paper presents a Network-on-Chip (NoC) design methodology for generating high quality interconnects for multi-core System-on-Chip architectures. The design process incorporates the main objectives of low power and high performance during topology synthesis. A rendezvous interaction performance analysis method is presented where Layered Queuing Network models are invoked to observe the asynchronous interactions between NoC components and identify possible performance degradation within the on-chip multi-core network. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of our proposed technique.

As technology continues to demand high performance, low power, and integration density, NoC system designers consider multiple aspects during the design phase. This paper addresses these issues and presents an NoC design methodology for generating high quality interconnects for custom Multiprocessor System-on-Chip (MPSoC) architectures. Our design methodology incorporates the main objectives of power and performance during topology synthesis while employing both analytical and simulation based automated techniques. A rendezvous interaction performance analysis method is presented where Layered Queuing Network models are invoked to observe the asynchronous interactions between NoC components and identify possible performance degradation in the on-chip network. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of our proposed technique.

This paper presents a power and performance multi-objective Tabu Search based technique for designing application-specific Network-on-Chip architectures. The topology generation approach uses an automated technique to incorporate floorplan information and attain accurate values for wirelength and area. The method also takes dynamic effects such as contention into account, allowing performance constraints to be incorporated during topology synthesis. A new method for contention analysis is presented in this work which makes use of power and performance objectives using a Layered Queuing Network (LQN) contention model. The contention model is able to analyze rendezvous interactions between NoC components and alleviate potential bottleneck points within the system. Several experiments are conducted on various SoC benchmark applications and compared to previous works.