Aggressively monitoring and tracking system-on-chip (SoC) performance under process/voltage/temperature (PVT) variations is essential for high-performance computing systems. This work observes that different chips of the same SoC design may have different PVT-to-delay sensitivities, which must be carefully considered for accurate chip performance tracking. A learning-based method is then proposed to fit critical path delay for different chips with different PVT-to-delay sensitivities. Experimental results based on the fabricated chip samples of a 7nm SoC have justified the effectiveness of the proposed PVT-sensitive delay fitting method. Compared with the state-of-the-art, our method can achieve excellent performance tracking accuracy when the chip performance is dominated by different critical paths under different PVT conditions.

Monitoring system-on-chip performance under process, voltage, and temperature (PVT) variations is very challenging, especially when the parasitic effects dominate the whole chip performance in advanced process nodes. Most of the previous works presented the performance monitoring methodologies based on known/predicted candidates of critical paths under different operating conditions. However, those methodologies may fail when the critical path is misrecognized or mispredicted. This paper proposes a novel machine-learning based chip performance monitoring methodology to accurately match the chip performance without requiring the information of critical paths under various PVT conditions. The experimental results based on measured chip performance show that the proposed methodology can achieve 98.5% accuracy in the worst case under wide-range PVT variations.