This work introduces SENSOTERIC, a multi-partner project that aims at leveraging the properties of emerging Reconfigurable Field Effect Transistors (RFETs) to develop a sensor platform. RFETs will be used for a generic sensor interface and for a dedicated transducer element. In the first case, our goal is to develop an analog front-end interface that can be tuned at runtime to adapt to different environmental conditions and be used in a broad spectrum of applications. This feature shall be enabled by the polarity-control and negative differential resistance characteristics of the reconfigurable devices employed, that are co-integrable on industrial CMOS processes such as 22 nm FDSOI. In the second case, we want to exploit the intrinsic nature of these doping-free devices to yield better 1/f noise performances when compared to classic CMOS transducers. Moreover, the presence of un-gated areas on top of the channel of these devices makes them the perfect candidates to be functionalized. In this early-stage overview of the project, we will introduce the key features and the vision that make SENSOTERIC a unique contribution towards smart sensing solutions in environmental monitoring and healthcare.

This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and ultra-efficient class of ANN accelerators, the neural network compute cube$(N^{2}C^{2})$, which is specifically designed to execute complex machine learning tasks in a 3D technology, in order to provide the high computing power and ultra-high efficiency needed for future edgeAI applications. We showcase its effectiveness by targeting the challenging class of Transformer ANNs, tailored for Automatic Speech Recognition and Machine Translation, the two fundamental components of speech-to-speech translation. To gain the full benefit of the accelerator design, we develop disruptive vertical transistor technologies and execute design-technology-co-optimization (DTCO) loops from single device, to cell and compute cube level. Further, a hardware-software-co-optimization is executed, e.g. by compressing the executed speech recognition and translation models for energy efficient executing without substantial loss in precision.

The vertical nanowire field effect transistor (VN-WFET) is an emerging technology that promises to improve the sustainability of future transistor scaling beyond the limitations of conventional lateral devices. With its 3D gate-all-around (GAA) architecture, such a technology enables designs with improved energy-efficiency as well as reduced footprint and thus interconnect capacitance. In this work, and based on the compact model of a real VNWFET device, we present the design flow for the generation of a standard cell library starting from the circuit and physical design of logic cells to logic synthesis based on the VNWFET technology. The results on the synthesized benchmark cells, as compared against 45nm and 65nm CMOS libraries, demonstrate a significant decrease in the average dynamic power consumption and delay values up to 71X and 34X respectively, with anaveragearea gain of up to 5X. However, an increase in leakage power consumption (up to 2X on average) was also observed.

Vertical Nanowire Junction-less Transistors (VN-WFET) are a promising technology for designing energy-efficient neural networks. This work presents the first results for 3D VNWFET logic cell design taking into account the influence of intra-cell parasitic interconnects on circuit performances. The proposed methodology is used to investigate the performance of a CMOS inverter through co-simulation of the VNWFET SPICE compact model coupled with the circuit parasitic netlist extracted from 3D TCAD simulations using a standard circuit simulator.