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Andrew Cheung

dblp:290/6541 · DBLP profile ↗
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3ranked-venue papers
0as first author
2since 2021 · last 2024
0009-0006-0661-2640ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Artificial intelligence and machine learning · 1Software engineering, systems software and programming languages · 1 · 1 since 2021Databases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%
Software engineering, system software, and programming languages
1 paper
Program synthesis and code generation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › logic synthesis › technology mapping
FPGA technology mapping
0.812024
FPGA Technology Mapping Using Sketch-Guided Program Synthesis · ASPLOS (2) 2024
Electronic design automation
logic synthesis
0.812024
FPGA Technology Mapping Using Sketch-Guided Program Synthesis · ASPLOS (2) 2024
Electronic design automation › logic synthesis
technology mapping
0.812024
FPGA Technology Mapping Using Sketch-Guided Program Synthesis · ASPLOS (2) 2024
Program synthesis and code generation › syntax-guided synthesis
sketch-based synthesis
0.212024
FPGA Technology Mapping Using Sketch-Guided Program Synthesis · ASPLOS (2) 2024

Methods — techniques the papers use, named apart from their topics

sketch templates · 1.5semantics extraction from HDL · 1.5
YearPublicationVenuePosition
2024 FPGA Technology Mapping Using Sketch-Guided Program Synthesis
abstract
FPGA technology mapping is the process of implementing a hardware design expressed in high-level HDL (hardware design language) code using the low-level, architecture-specific primitives of the target FPGA. As FPGAs become increasingly heterogeneous, achieving high performance requires hardware synthesis tools that better support mapping to complex, highly configurable primitives like digital signal processors (DSPs). Current tools support DSP mapping via handwritten special-case mapping rules, which are laborious to write, error-prone, and often overlook mapping opportunities. We introduce Lakeroad, a principled approach to technology mapping via sketch-guided program synthesis. Lakeroad leverages two techniques---architecture-independent sketch templates and semantics extraction from HDL---to provide extensible technology mapping with stronger correctness guarantees and higher coverage of mapping opportunities than state-of-the-art tools. Across representative microbenchmarks, Lakeroad produces 2--3.5× the number of optimal mappings compared to proprietary state-of-the-art tools and 6--44× the number of optimal mappings compared to popular open-source tools, while also providing correctness guarantees not given by any other tool.
Gus Henry Smith, Benjamin Kushigian, Vishal Canumalla, Andrew Cheung, Steven Lyubomirsky, Sorawee Porncharoenwase, René Just, Gilbert Louis Bernstein, Zachary Tatlock
ASPLOS (2)4
2024 Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface
abstract
Ideally, accelerator development should be as easy as software development. Several recent design languages/tools are working toward this goal, but actually testing early designs on real applications end-to-end remains prohibitively difficult due to the costs of building specialized compiler and simulator support. We propose a new first-in-class, mostly automated methodology termed “3LA” to enable end-to-end testing of prototype accelerator designs on unmodified source applications. A key contribution of 3LA is the use of a formal software/hardware interface that specifies an accelerator’s operations and their semantics. Specifically, we leverage the Instruction-level Abstraction (ILA) formal specification for accelerators that has been successfully used thus far for accelerator implementation verification. We show how the ILA for accelerators serves as a software/hardware interface, similar to the Instruction Set Architecture for processors, that can be used for automated development of compilers and instruction-level simulators. Another key contribution of this work is to show how ILA-based accelerator semantics enables extending recent work on equality saturation to auto-generate basic compiler support for prototype accelerators in a technique we term “flexible matching.” By combining flexible matching with simulators auto-generated from ILA specifications, our approach enables end-to-end evaluation with modest engineering effort. We detail several case studies of 3LA, which uncovered an unknown flaw in a recently published accelerator and facilitated its fix.
Bo-Yuan Huang 0001, Steven Lyubomirsky, Yi Li 0085, Mike He, Gus Henry Smith, Thierry Tambe, Akash Gaonkar, Vishal Canumalla, Andrew Cheung, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik
ACM Trans. Design Autom. Electr. Syst.9
2018 Toward a Semantic Concordancer
abstract
Concordancers are an accepted and valuable part of the tool set of linguists and lexicographers.They allow the user to see the context of use of a word or phrase in a corpus.A large enough corpus, such as the Corpus Of Contemporary American English, provides the data needed to enumerate all common uses or meanings.One challenge is that there may be too many results for short search phrases or common words when only a specific context is desired.However, finding meaningful groupings of usage may be impractical if it entails enumerating long lists of possible values, such as city names.If a tool existed that could create some semantic abstractions, it would free the lexicographer from the need to resort to customized development of analysis software.To address this need, we have developed a Semantic Concordancer that uses dependency parsing and the Suggested Upper Merged Ontology (SUMO) to support linguistic analysis at a level of semantic abstraction above the original textual elements.We show how this facility can be employed to analyze the use of English prepositions by non-native speakers.We briefly introduce condordancers and then describe the corpora on which we applied this work.Next we provide a detailed description of the NLP pipeline followed by how this captures detailed semantics.We show how the semantics can be used to analyze errors in the use of English prepositions by non-native speakers of English.Then we provide a description of a tool that allows users to build seman-tic search specifications from a set of English examples and how those results can be employed to build rules that translate sentences into logical forms.Finally, we summarize our conclusions and mention future work.
Adam Pease, Andrew Cheung
GWC2