To avoid corruption of user data, predictive testing methods have been proposed to identify SRAMs likely to fail in the near future due to aging. These methods use aggressive operating conditions, e.g., adjustments to wordline voltages or the power supply voltage, that are calibrated to provide high coverage of SRAMs likely to fail in the near future, but end up with some over-testing, i.e., spuriously identifying some chips as likely to fail. We first present our study which discovered that a large fraction of over-tested chips fail due to read faults triggered during read-1 operations. Our analysis identifies asymmetric aging in SRAM cells, which are more likely to store zeros, as the root cause for this. We build on this discovery to propose an asymmetric predictive testing method which performs writes using normal voltages, read-0 at aggressive voltages, and read-1 at less aggressive voltages. We demonstrate that this method significantly reduces over-testing by over $3 \times$ to $5 \times$, for low limits on under-testing. We also propose and use a new statistical sampling and simulation method to enable fast convergence and accurate evaluation of asymmetric predictive testing.

We develop a method to estimate lifetime performance, yield, and power for Static Random-Access Memories (SRAMs) that captures the combination of process variations and aging. Using this method, we design and validate predictive tests to detect future aging failures. We use the results of predictive tests to reconfigure dynamic voltage and frequency scaling (DVFS) to reduce aging failures at minimal energy and latency overheads.

In the era beyond the end of physical scaling of CMOS, growing attention is being paid to Superconducting electronics (SCE), especially Rapid Single Flux Quantum (RSFQ) logic due to its high-performance and low power consumption. In [1]–[3], static and delay fault models, corresponding automatic test pattern generator (ATPG) for testing these faults, and a scan architecture are developed. However, test pattern application involves moving patterns and responses via long wires from the test equipment at room temperature to the chip under test in liquid helium, which severely reduces the test clock frequency. At the same time, due to the high clock frequency of this technology, at-speed test is necessary for testing delay faults.In this paper, we present a scan-based BIST for RSFQ circuits which performs at-speed self-test including pseudo random pattern generation and response compression. We show that existing designs of pattern generators cannot be directly used for RSFQ and present new designs. Based on the scan architecture in [3], we design a new control strategy for at-speed self-test. We demonstrate that our new architecture supports testing at low overheads.

Superconducting electronics (SCE), especially Rapid Single Flux Quantum (RSFQ) logic, is being developed due to its high-performance and low power. In [1] –[3], we developed new static and delay fault models and an efficient automatic test pattern generator (ATPG) for testing both delay and static faults in RSFQ logic. However, test pattern application involves moving patterns and responses via long wires from the test equipment at room temperature to the chip under test in liquid helium. Due to the high cost associated with large numbers of such wires, testing is extremely expensive in absence of design for testability.We present a scan architecture for RSFQ circuits which enables the application of a large number of test patterns. Due to the unique characteristic of RSFQ, this scan architecture includes completely new scan cell design and a new scan control strategy. The on-chip test control logic enables scan chain to shift in test patterns from the test equipment at room temperature via a small number of wires, apply the pattern to the chip under test in parallel and at speed, and shift out the corresponding test response for checking. We demonstrate that our new scan architecture supports testing at low overheads.

Every well-known march test for memories was generated to efficiently achieve 100% coverage of a target set of fault types. The question we pursue is: What to do if 100% coverage of the given target set cannot be achieved under tight constraints on test cost? We first study an obvious option: Remove some fault types from the given target set until a new or well-known test can cover 100% of the remaining fault types under the given test cost constraint. We find that this approach leaves significant room for improvement. We then pursue a different option and develop a new method which uses the original target set of fault types and generates a march test that maximizes the fault coverage under the given tight constraint on test cost. Our method generates fault-coverage maximizing tests for a wide range of target sets of fault types. A comparison with well-known march tests with equal lengths demonstrates that our new march tests provide significantly higher coverage for various sets of fault types. Importantly, our new march tests provide graceful decrease in fault coverage as we tighten constraints on test length. Hence our method and new march tests enable tradeoffs between test quality and test cost and provide a new direction of memory test research focused on fault-coverage-maximization.

Superconducting digital electronics, especially Single Flux Quantum (SFQ), has emerged as a promising beyond-CMOS technology with Josephson junctions (JJ) as the active device. It has the potential to meet the booming demands of lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Despite these promises, scaling SFQ circuits remains a serious challenge that motivates the support of multiple SFQ clock domains. Towards this end, this paper analyzes the impact of setup time violations and metastability in SFQ circuits comparing the derived analytical models to their CMOS counterparts. It also proposes new techniques to reduce the average latency in metastability-tolerant SFQ synchronizers, and evaluates their effects on the layout and critical margin of the design. It further extends the proposed model to estimate the Mean Time Between Failure (MTBF) of flip-flop-based synchronizers and shows that their MTBF with the current feature sizes is unaffected by noise, similar to CMOS. Finally, it curve fits this model to simulations using the state-of-the-art SFQ5ee process and shows that a two-flop SFQ synchronizer with a clock frequency of 25 GHz has an estimated MTBF of ~106years.