This paper presents the efficient systematic methods for modeling and analysis of spike signal sequence in crossbar arrays for neuromorphic computing chips. A novel spike signal sequence is proposed, where the ideal spike sequence with only spike time information in the original spiking neural network (SNN) algorithm is mapped onto actual spike waveform by stitching neighboring sequential spikes together with certain overlaps. We thoroughly investigate and analyze the performance of the input encoding as well as the implementation of spike timing dependent plasticity (STDP)-based SNN on memristor crossbar arrays with the proposed spike signal sequence. A detailed circuit model of a crossbar array, consisting of resistance, capacitance and inductance derived by the partial equivalent element circuit (PEEC) method, is created to simulate the training process of SNN. The proposed spike signal sequence is demonstrated that is able to achieve accurate input encoding as well as high recognition accuracy when it is used to perform the classification task on MNIST handwritten digits. The spike signal sequence is further analyzed and assessed in terms of the main factors affecting its encoding accuracy and the parasitic effects of crossbar arrays on its robustness.

This paper provides a comprehensive study of signal integrity issues in RRAM-based neuromorphic chip crossbar arrays due to interconnect parasitic. First, the parasitic parameters of the crossbar array are calculated by the partial equivalent element circuit (PEEC) method with an efficient unit-cell approach. Numerical experiments show that for a$50\times 50$array scale, this method consumes only 1.5% of the calculation time of the commercial software based 3D model, which translates to a calculation speed up of 72 times. Moreover, the PEEC circuit simulation results match well with those of the 3D model. Then, we investigate the effects of parasitic parameters such as capacitance and inductance, as well as the feature size of the crossbar array on signal integrity. All of them will lead to corresponding changes in parasitic effects, which in turn result in the most common signal integrity issues such as crosstalk, time delay and mutual capacitive coupling induced sneak path problem. Different from other studies, the excitation used in this paper is the neural spike signal generated by the Izhikevich neuron model, which is both rich in dynamic characteristics and high in computational efficiency. Finally, based on the study we propose a simple but effective design scheme for reduction of signal distortion, which can provide valuable design guidance for neuromorphic systems to achieve high performance and high computational accuracy.

This article presents a novel circuit modeling method for online training and testing process of the neuromorphic chip crossbar array based on the resistive random access memory (RRAM). A modified RRAM compact model is developed to realize the fast and accurate update of multiple conductance levels. Two training mechanisms with and without write-verify scheme are modeled and investigated for classifying MNIST handwritten digits and both achieve a good recognition accuracy of more than 96%. The parasitic model of the unit cell of interconnects is constructed by the domain decomposition method (DDM) and the partial equivalent element circuit (PEEC) method, which is suitable to build up a crossbar array of any size. The impact of parasitic effects of interconnects on the recognition accuracy with and without write-verify scheme is analyzed and compared. The weights trained with write-verify scheme show better robustness to parasitic noises but training with write-verify scheme spends a longer time processing the same amount of data.