Reinforcement learning (RL) has become a key enabler for realizing adaptive and autonomous decision-making in next-generation AI-driven wireless networks, enabling real-time optimization of transmission strategies to counter jamming attacks. However, this adaptability also introduces critical vulnerabilities since the reliance of RL agents on environmental feedback renders them susceptible to deception, particularly when adversaries manipulate the environment in order to mislead the learning process. Yet, even though prior research considered adversarial jamming with white or grey-box access to the RL agent, the challenge of black-box jamming, where the jammer adapts without explicit feedback on its impact, remains largely unexplored. With this motivation, the present contribution addresses a practical adversarial scenario where a smart anti-jamming agent does not just resist jamming but actively exploits jamming signals to increase its throughput, especially as jamming attacks intensify. Defeating such an adaptive agent is particularly challenging in black-box settings, where the jammer has no knowledge of the link’s internal mechanisms or reward structure. In this context, we systematically benchmark a variety of advanced reactive jamming strategies, including both interaction-driven and optimization-driven approaches, under these realistic constraints. The achieved results indicate that adaptive, learning-driven jammers can reliably force even intelligent anti-jamming links into suboptimal operation, causing substantial throughput loss while consuming significantly less jamming power than conventional reactive jamming attacks. These findings reveal a fundamental vulnerability in RL-driven cognitive networks and highlight the urgent call for more resilient learning frameworks in order to secure next generation wireless systems.

The integration of Mobile Edge Computing (MEC) and Wireless Power Transfer (WPT), which is usually referred to as Wireless Powered Mobile Edge Computing (WP-MEC), has been recognized as a promising technique to enhance the lifetime and computation capacity of wireless devices (WDs). Compared to the conventional battery-powered MEC networks, WP-MEC brings new challenges to the computation scheduling problem because we have to jointly optimize the resource allocation in WPT and computation offloading. In this paper, we consider the energy minimization problem for WP-MEC networks with multiple WDs and multiple access points. We design an online algorithm by transforming the original problem into a series of deterministic optimization problems based on the Lyapunov optimization theory. To reduce the time complexity of our algorithm, the optimization problem is relaxed and decomposed into several independent subproblems. After solving each subproblem, we adjust the computed values of variables to obtain a feasible solution. Extensive simulations are conducted to validate the performance of the proposed algorithm.

In FPGAs, the programmable interconnect is implemented by multiplexers (MUXes), which have a large impact on the area and delay. In academia, large MUXes are extensively used in intra and inter clusters, resulting in significant FPGA area overhead and load for routing wires. In this paper, we model the interconnect from routing wires and CLB feedbacks to LUT inputs as an input block (IB), and implement the IB and the switch block (SB) with the 2-level MUX topology. Applying the 2-level MUX topology in FPGA routing architecture enables us to explore a larger design space for the area and delay, because the 2-level MUX topology can tradeoff between MUX sizes, connectivity degree, and the input bandwidth. We carefully design a baseline 2-level MUX routing architecture and evaluate it by running place and route experiments with VTR benchmarks. To optimize the baseline 2-level MUX routing architecture, we explore one design parameter at a time by keeping others fixed and perform subsequent explorations based on previous optimal design parameters. The results show that the optimized 2-level MUX routing architecture can achieve 1% shorter critical path delay (CPD) at the cost of 3% area overhead compared to the CB-SB FPGA architecture with 1-level MUX topology.

Routing architecture has a significant impact on the area, critical path delay and power consumption of modern FPGAs. The most common routing architecture of island-style FPGAs in academia is the CB-SB model, which is not effective to model complex routing architectures in modern FPGAs. To improve the routability and performance of the existing routing model, we propose a new routing model called General Routing Block (GRB) to model complex commercial FPGAs. In the proposed model, all routing resources can be divided into three modules: general switch block (GSB), input connection block (ICB) and output connection block (OCB). The GSB and ICB are extended from the SB and CB with more flexible and richer connections. The OCB is a new module that provides novel connections for the LB output pins. We support bent wire architecture to reduce the delay, and two-level MUXes with output sharing to achieve a better trade-off between the area and flexibility. Moreover, to explore the trade-offs of different design spaces and find better architectures, an architecture exploration platform based on the simulated annealing algorithm is proposed to efficiently explore the enormous design space specified by a set of parameters. The results of global design space exploration show that the architecture with the proposed GRB model reduces the critical path delay by 15.5% and area-delay product by 14.8% compared to the length-4 CB-SB architecture based on the VTR benchmarks. After further local subspace explorations, the best architecture can achieve an 18.7% improvement on the critical path delay and a 23.8% improvement on the area-delay product, which represents a significant improvement over other routing architectures.