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Cheolgyu Jin

dblp:290/8998 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Hardware security and side channels · 81% Cryptographic primitives and cryptanalysis · 19%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › side-channel attack › cache side-channel attacks
cache timing attack
0.512021
Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery · HPCA 2021
Hardware security and side channels
side-channel attack
0.512021
Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery · HPCA 2021
Cryptographic primitives and cryptanalysis › block cipher cryptanalysis
AES key recovery
0.112021
Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery · HPCA 2021
Hardware security and side channels › side-channel attack › GPU side channel
GPU side-channel attack
0.112021
Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery · HPCA 2021
Hardware security and side channels
side-channel countermeasures
0.112021
Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery · HPCA 2021
Cryptographic primitives and cryptanalysis
symmetric cryptography
0.112021
Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery · HPCA 2021
YearPublicationVenuePosition
2021 Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery
abstract
Given the parallel processing capabilities of Graphics Processing Units (GPUs), many applications are exploiting GPUs and cryptographic systems have also begun to leverage GPUs to accelerate encryption/decryption. Recent work has identified how microarchitectural side-channel attacks can be carried out on AES (Advanced Encryption Standard) by exploiting the SIMT characteristics and memory coalescing of GPUs. In this work, we first show that previously proposed correlation-based side-channel attacks are not feasible on modern GPUs that support narrower data-cache accesses via a sectored-cache microarchitecture-resulting in memory accesses from different levels of the memory hierarchy. In comparison, we identify how negative timing correlation can occur in modern GPUs when data is fetched from different levels of the cache hierarchy. We then propose Trident - a hybrid cache-collision timing attack on GPUs that can fully recover all AES key bytes on modern GPUs. Cache collisions in GPUs present challenges due to the large number of threads and the number of samples required. To address these challenges, Trident consists of three different components - negative timing correlation, cache-collision attack, and chosen plaintext attack. We leverage the negative timing correlation to recover earlier key bytes of AES while exploiting cache-collision attacks for the latter AES key bytes. To enable GPU cache collision attacks, we exploit memory coalescing to control the number of memory accesses through chosen-plaintext attacks to significantly reduce the number of timing samples needed. Our proposed Trident attack results in over 10× reduction in the number of samples needed to recover the key bytes compared with prior work, while still being successful in full AES key recovery in modern GPUs. We also propose TridentShield - a latency-based countermeasure to the Trident attack that minimizes throughput degradation in GPUs.
Jaeguk Ahn, Cheolgyu Jin, Minsoo Rhu, Yunsi Fei, David R. Kaeli, John Kim 0001
HPCA2