This work presents the 1.2 V Low-Dropout Regulator (LDO) designed in a standard 65 nm CMOS technology using data obtained from experimental verification of 9 prototype chips. The measurement of standard parameters that were evaluated included Load Regulation (LDR) in the output current I out range from$\mathbf{1} \boldsymbol{\mu} \mathbf{A}$to$\mathbf{3 0 0} \boldsymbol{\mu} \mathbf{A}$, Line Regulation (LNR) at$\boldsymbol{I}_{\text {out }}$of$100 \mu ~\mathrm{A}$and$300 \mu ~\mathrm{A}$, Drop-Out voltage and PSRR parameter. In addition, the presented LDO dispose of a Slew-Rate Enhancement function, which can be activated externally. In all cases of this feature activation, the measurement proved its expected and correct function with reducing the settling time value and, depending on the direction of the output current change, also the voltage value for overshoot or undershoot.

This paper presents tunable voltage reference (TVR) designed in a standard general purpose 65nm CMOS technology. Designed circuit is based on two-transistor (2T) voltage reference (VR) with digitally controlled operational amplifier (OPAMP). Developed TVR provides stable output voltage from 0.38 V to 1.1 V with non-linear tuning step under 0.5% of the output voltage (from 1.9 mV to 2.9 mV). The supply voltage in the range from 0.91 V to 1.5 V is used. The circuit offers parameter PSRR = -53.59 dB (at 1 kHz) and line regulation (LNR) of 0.35% in the worst case. The required area is 0.0185 mm2. The proposed TVR was used to precise frequency tuning of oscillator. Provided results are obtained from both simulations and measurement of the manufactured ASIC prototype.

This work presents a dedicated method of analog integrated circuit (IC) autocalibration, which was used to calibrate a voltage reference with the output voltage value of 96 mV . The reference accuracy might be significantly influenced by fluctuations in the manufacturing process. The essence of this technique is to suppress this undesired influence of process variations in terms of the corner conditions of 130 nm CMOS technology. All analog parts of the proposed autocalibration system are presented at the transistor level. The output of the calibration subcircuit is a digital signal controlling the autocalibration.

This paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. The proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is built-in with the calibrated FDDA, and the whole integrated system is able to operate with only 0.4 V power supply. The effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, process corners and ageing analyses performed for the temperature range from -20° C to 85° C. The work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. The proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. The less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 μV to 167 μV). The concept proposed in this work utilizes advanced high precision calibration algorithm.