Chuanpei Xu

dblp:291/6589 · DBLP profile ↗
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4ranked-venue papers
0as first author
4since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 since 2021Artificial intelligence and machine learning · 1 · 1 since 2021
YearPublicationVenuePosition
2026 Topology Optimization of 3-D NoC for High-Speed Data Acquisition Systems via Deep Reinforcement Learning
abstract
The deployment of high-speed data acquisition systems (HS-DAQs) on 3-D network-on-chip (3-D NoC) requires the real-time transmission of large volumes of data across the network. However, conventional generic topology structures are difficult to adapt effectively to the specific communication characteristics of such systems, leading to degraded overall transmission efficiency. This article proposes a topology optimization methodology for 3-D NoC oriented toward HS-DAQ systems. The topology adjustment process is formulated as a sequential optimization task, and deep reinforcement learning is employed to progressively refine the network connections to better match the system communication load. A pruning–regrowth mechanism is introduced to reconstruct critical links, thereby achieving a balance between latency performance and area overhead. In addition, an action candidate set combined with a dual-level$\varepsilon $-greedy strategy is adopted to enhance training stability and search efficiency in large-scale action spaces. Experimental results on HS-DAQ systems of different scales (16–48 nodes) demonstrate that, compared with the 3-D Mesh NoC and 3-D PC-NoC, the optimized network topology reduces the average latency by approximately 4.2%–14.3% and 11.7%–30.3%, the maximum path latency by about 13.6%–19.7%, and the edge area by 27.8%–33.3% and 5.6%–14.7%, respectively.
Yunhui Deng, Chuanpei Xu, Wei Mo, Chunting Wan
IEEE Trans. Very Large Scale Integr. Syst.2
2025 Path planning algorithm for data acquisition system based on 3D network-on-chip
Yunhui Deng, Chuanpei Xu
Integr.2
2023 A decomposition-based two-stage online scheduling approach and its integrated system in the hybrid flow shop of steel industry
Sheng-Long Jiang, Chuanpei Xu, Long Zhang 0016
Expert Syst. Appl.2
2021 Design of time-interleaved data acquisition system based on Network on Chip
abstract
Abstract In order to solve the existing problems of time‐interleaved data acquisition system's poor scalability, limited acquisition channels, and complicated clock system based on System on Chip(SoC), this work presents a novel method of high‐speed data acquisition based on Network on Chip (NoC) communication architecture and time‐interleaved principle. Six analog‐to‐digital data acquisition resource nodes are hooked up to the NoC according to the unified features of NoC router interface. The data acquisition controller controls the time‐interleaved acquisition's timing sequences and realizes the remote transmission of data through two Gigabit Ethernet resource nodes. Adding timestamp to the collected data of each channel can recover the waveform signal accurately. The experiment results show that the combination of NoC communication architecture and time‐interleaved data acquisition has a certain innovative significance.
Jiangwei Zhao, Chuanpei Xu
Concurr. Comput. Pract. Exp.2