The efficiency of validating complex System-on-Chips (SoCs) is contingent on the quality of the security properties provided. Generating security properties with traditional approaches often requires expert intervention and is limited to a few IPs, thereby resulting in a time-consuming and non-robust process. To address this issue, we, for the first time, propose a novel and automated Natural Language Processing (NLP)-based Security Property Generator (NSPG). Specifically, our approach utilizes hardware documentation in order to propose the first hardware security-specific language model, HS-BERT, for extracting security properties dedicated to hardware design. It is capable of phasing a significant amount of hardware specification, and the generated security properties can be easily converted into hardware assertions, thereby reducing the manual effort required for hardware verification. NSPG is trained using sentences from several SoC documentations and achieves up to 88% accuracy for property classification, outperforming ChatGPT. When assessed on five untrained OpenTitan hardware IP documents, NSPG aided in identifying eight security vulnerabilities in the buggy OpenTitan SoC presented in Hack@DAC 2022.

Quantum computers have demonstrated exponential speedup for certain computational tasks like integer factorization, molecular simulation, and machine learning, compared to the classical computers. One of the most challenging problems in quantum computing is quantum compilation, which involves the translation of a quantum circuit into a representation that adheres to the constraints imposed by the quantum hardware. However, this process of mapping the logical qubits to physical qubits incurs a significantly large search space, which needs to be analyzed to obtain the optimal mapping. A non-optimal mapping or compilation strategy introduces additional hardware overhead, thereby rendering inefficiency. Recently, researchers have proposed a technique to reduce the search space for efficient quantum compilation. However, this approach focuses on a generic solution involving only the physical architecture, and hence, as shown in our paper, often fails to incorporate the optimal solution in the reduced search space. To this end, we propose PERM and SGO (PAS), which, to the best of our knowledge, is the first quantum compilation strategy that facilitates a reduced search space comprising a more optimal solution in terms of additional CNOT gates compared to the existing technique. Our experimental evaluation using the MQT benchmarks demonstrates the efficacy of our approach, which furnishes up to 428x reduction compared to the unoptimized search space, and 57.1x reduction compared to existing research, while providing savings in terms of additional CNOT gates by up to 53.85%.

The extensive adoption of safety-critical applications in high-assurance environments, such as the automotive domain, has laid emphasis on safeguarding the reliability and Functional Safety (FuSa) of the Electrical and/or Electronic (E/E) components constituting such systems. Most modern automotive Systems-on-Chips (SoCs) comprise Analog and Mixed Signal (AMS) circuits, which are more susceptible to faults than their digital equivalents. However, their attributes of operating in the continuous signal region can be leveraged to perform early anomaly detection, which could facilitate the subversion of the eventual hardware failure state, thereby improving the FuSa of the system. To this end, we had proposed a novel unsupervised learning-based early anomaly detection framework catered to automotive AMS circuits (in ITC 2022). However, existing approaches to AMS FuSa violation detection are limited by pre-specified feature inputs, and lack rationale for identifying signals to be monitored to perform anomaly detection. To address these issues as well as further augment our original solution, in this paper, we propose a novel anomaly detection strategy that involves: (1) a genetic algorithm-based feature selection approach, (2) a novel signal selection algorithm that ascertains the best intermediate circuit signal, for furnishing enhanced anomaly detection accuracy, while reducing the associated detection latency, and (3) an explainable AI (XAI)-based framework that boosts user interpretability and transparency of the anomaly detection framework. This XAI approach, in turn, can be provided as feedback to the designer during circuit design and validation. The proposed approach is evaluated using case studies of two representative AMS circuits, which are prevalent in automotive SoCs. Our experimental analyses demonstrate that the proposed approach furnishes up to 100% detection accuracy and 2.3× reduction in detection time compared to our existing framework, in addition to providing insights by improving transparency of the anomaly detection framework, thereby exhibiting the efficacy of our solution.

The proliferation of deep learning algorithms has catalyzed their utilization to solve a multitude of real-world problems. Algorithms such as deep neural networks (DNNs) are compute- and power-intensive, thereby accentuating the development of hardware platforms like DNN inference accelerators. However, inference execution of large DNNs in resource-constrained environments induces energy bottlenecks in these accelerators. Since large DNNs consist of hundreds of millions of trained parameters, accessing them from the accelerator memory incurs substantial energy. To address this challenge, we propose HardCompress, which, to the best of our knowledge, is the first low-power solution that uses traditional compression strategies pertaining to commercial DNN accelerators in resource-constrained IoT edge devices. The three-step approach involves hardware-based post-quantization trimming of weights, followed by their dictionary-based compression and subsequent decompression by a low-power hardware engine during inference in the accelerator. We evaluate the proposed solution on lightweight networks trained on the MNIST dataset, the compact model trained on the CIFAR-10 dataset, and large DNNs trained on the ImageNet dataset. Performance of HardCompress at different quantization levels has been analyzed. Furthermore, to quantify the effectiveness of the proposed solution, an energy framework that contrasts the DRAM energies of the original and HardCompressed models has been developed. Finally, a fault injection framework which compares the fault resilience of the original model with its HardCompressed counterpart is also proposed. Our results exhibit that HardCompress, without any performance degradation in large DNNs, furnishes a maximum compression of 99.27%, equivalent to$137\times $reduction in memory footprint and 0.07 J for 8-bit quantization in the systolic array-based DNN accelerator. Furthermore, our proposed low-power decompression engine incurs an area overhead of only 0.02%; thus, enabling HardCompress’ utilization in resource-constrained environments.

With the proliferation of safety-critical applications in the automotive domain, it is imperative to guarantee the functional safety of circuits and components constituting automotive systems, e.g., the electrical and/or electronic subsystems in automotive vehicles. Analog and Mixed-Signal (AMS) circuits, prevalent in such systems, are more susceptible to faults than their digital counterparts, due to advanced manufacturing nodes, parametric perturbations, environmental stress, etc. However, their continuous signal characteristics provide an opportunity for early anomaly detection, which in turn, facilitates the deployment of safety mechanisms to prevent eventual system failure. Towards this end, we propose a novel unsupervised machine learning-based framework to perform early anomaly detection in AMS circuits. Our approach involves anomaly injection in various circuit locations and individual components to develop a training dataset encompassing a wide range of possible anomalous scenarios, feature extraction from observation signals, and clustering algorithms to facilitate anomaly detection. To this end, we propose a novel centroid selection technique for the unsupervised learning algorithms, which is tailored for detecting anomalies in AMS circuits. This approach furnishes high fidelity anomaly detection by identifying the ideal cluster centers corresponding to anomalous and non-anomalous signals. Furthermore, time series-based analysis is proposed to improve and expedite the anomaly detection performance. We evaluated our solution using a case study of two AMS circuits commonly present in automotive systems-on-chips. Our experimental results exhibit that the proposed approach furnishes up to 100% accuracy. Additionally, the time series-based technique reduces the anomaly detection latency by 5×, thereby demonstrating the efficacy of our solution.