Transformer models represent the cutting edge of Deep Neural Networks (DNNs) and excel in a wide range of machine learning tasks. However, processing these models demands significant computational resources and results in a substantial memory footprint. While In-memory Computing (IMC) offers promise for accelerating Vector-Matrix Multiplications (VMMs) with high computational parallelism and minimal data movement, employing it for other crucial DNN operators remains a formidable task. This challenge is exacerbated by the extensive use of complex activation functions, Softmax, and data-dependent matrix multiplications (DMMuls) within Transformer models. To address this challenge, we introduce a Reconfigurable Analog Computing Engine (RACE) by enhancing Analog Content Addressable Memories (ACAMs) to support broader operations. Based on the RACE, we propose the RACE-IT accelerator (meaning RACE for In-memory Transformers) to enable efficient analog-domain execution of all core operations of Transformer models. Given the flexibility of our proposed RACE in supporting arbitrary computations, RACE-IT is well-suited for adapting to emerging and non-traditional DNN architectures without requiring hardware modifications. We compare RACE-IT with various accelerators. Results show that RACE-IT increases performance by 453× and 15×, and reduces energy by 354× and 122× over the state-of-the-art GPUs and existing Transformer-specific IMC accelerators, respectively.

The recent success of machine learning (ML) models has led to increasing demands for model explanations - why a result was given - along with model predictions. Tree-based ML models are considered more explainable than deep neural networks and higher performers in several domains. However, algorithms computing model explanations are irregular and scale poorly with model size. While many custom accelerators for training and inference have been proposed, little attention has been paid to accelerating model explanations. This lack of explanatory capability has limited the use of these models for real-time decision-making systems in critical fields such as healthcare, autonomous operation and cybersecurity.

In-memory computing is, in current literature, the most common paradigm used to counteract the Von-Neumann bottleneck, proposing the use of memory elements to define complex input-output relations of the computing kernels. While in classical CMOS computing a similar paradigm can be implemented with look-up tables (LUT), this solution is power and area-hungry. This paper presents the use of Quaternary Content-Addressable Memories (QCAMs), a generalization of the Ternary Content-Addressable Memories (TCAMs), for implementing boolean functions. Content-Addressable Memories can be used as a building block for in-memory processing, using the states of the cells to define a ${\mathbb{B}^{\text{N}}} \to {\mathbb{B}^{\text{M}}}$ function which projects the search word into a new string of bits. The quaternary alphabet allows to represent a more complex function space with respect to the TCAMs while using the same number of cells, enhancing area, power consumption and latency performances achieved when representing arbitrary functions with the CAM hardware. For comparison, it can be demonstrated that QCAMs represent arbitrary Boolean functions with half the number of cells than that would be needed in a standard TCAM implementation, and a ×10 smaller area with respect to SRAM-based LUTs. Along with the table of states and a toy example where the QCAM states are used to define the product among two 2-bit precision real values, this paper presents multiple circuit schemes and encoding schemes for memristor-based QCAMs.