EDBT 2026 Demo / reviewers in the wild / expert
Wenxuan Pan
dblp:292/8619
· DBLP profile ↗
5ranked-venue papers
2as first author
5since 2021 · last 2026
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Artificial intelligence and machine learning · 2 · 1 first-author · 2 since 2021Systems, architecture and hardware · 1 · 1 since 2021Computer networks · 1 · 1 first-author · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 since 2021Graphics, computer vision, multimedia, augmented reality and games · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 100% | |
| Computer networks
1 paper |
Wireless sensing and localization · 62% Physical-layer communications · 38% | |
| Artificial intelligence
1 paper |
Learning paradigms · 50% Deep learning architectures and training · 50% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Wireless sensing and localization › indoor localization
visible light positioning |
1.0 | 1 | 2026 | Visible Light Positioning With Lamé Curve LEDs: A Generic Approach for Camera Pose Estimation · IEEE Trans. Commun. 2026 |
Compilers and program optimization › instruction scheduling
instruction-level parallelism |
0.9 | 1 | 2025 | GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving · DAC 2025 |
Compilers and program optimization
instruction scheduling |
0.9 | 1 | 2025 | GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving · DAC 2025 |
GPUs and heterogeneous computing
GPU kernel optimization |
0.9 | 1 | 2025 | GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving · DAC 2025 |
GPUs and heterogeneous computing › GPU kernel optimization
kernel fusion |
0.9 | 1 | 2025 | GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving · DAC 2025 |
Machine learning › Learning paradigms
continual learning |
0.7 | 1 | 2023 | Enhancing Efficient Continual Learning with Dynamic Structure Development of Spiking Neural Networks · IJCAI 2023 |
Machine learning › Deep learning architectures and training
spiking neural network |
0.7 | 1 | 2023 | Enhancing Efficient Continual Learning with Dynamic Structure Development of Spiking Neural Networks · IJCAI 2023 |
Physical-layer communications › optical wireless communication › visible light communication
LED-based positioning |
0.3 | 1 | 2026 | Visible Light Positioning With Lamé Curve LEDs: A Generic Approach for Camera Pose Estimation · IEEE Trans. Commun. 2026 |
Physical-layer communications › optical wireless communication
visible light communication |
0.3 | 1 | 2026 | Visible Light Positioning With Lamé Curve LEDs: A Generic Approach for Camera Pose Estimation · IEEE Trans. Commun. 2026 |
Methods — techniques the papers use, named apart from their topics
control flow graph · 1.7PTX-level instruction weaving · 1.7perspective-n-points · 1.0nonlinear least squares · 1.0structural plasticity · 0.7neuron growth and pruning · 0.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Visible Light Positioning With Lamé Curve LEDs: A Generic Approach for Camera Pose EstimationabstractCamera-based visible light positioning (VLP) is a promising technique for accurate and low-cost indoor camera pose estimation (CPE). To reduce the number of required light-emitting diodes (LEDs), advanced methods commonly exploit LED shape features for positioning. Although interesting, they are typically restricted to a single LED geometry, leading to failure in heterogeneous LED-shape scenarios. To address this challenge, this paper investigates Lamé curves as a unified representation of common LED shapes and proposes a generic VLP algorithm using Lamé curve-shaped LEDs, termed LC-VLP. In the considered system, multiple ceiling-mounted Lamé curve-shaped LEDs periodically broadcast their curve parameters via visible light communication, which are captured by a camera-equipped receiver. Based on the received LED images and curve parameters, the receiver can estimate the camera pose using LC-VLP. Specifically, an LED database is constructed offline to store the curve parameters, while online positioning is formulated as a nonlinear least-squares problem and solved iteratively. To provide a reliable initialization, a correspondence-free perspective-n-points (FreePnP) algorithm is further developed, enabling approximate CPE without any pre-calibrated reference points. The performance of LC-VLP is verified by both simulations and experiments. Simulations show that LC-VLP outperforms state-of-the-art methods in both circular- and rectangular-LED scenarios. Compared to a perspective arcs algorithm, LC-VLP can achieve reductions of both over 30% in average position and rotation errors. Experiments further show that LC-VLP can achieve an average position accuracy of less than 4 cm. Wenxuan Pan, Yang Yang 0057, Dong Wei 0002, Yao Nie |
IEEE Trans. Commun. | 1 |
| 2025 | GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow WeavingabstractGPUs have been heavily utilized in diverse applications, and numerous approaches, including kernel fusion, have been proposed to boost GPU efficiency through concurrent kernel execution. However, these approaches generally overlook the opportunities to mitigate warp stalls and improve instruction level parallelism (ILP) in inter-kernel resource sharing. To address this issue, we introduce GOPTX, a novel design for kernel fusion that improves ILP through deliberate weaving instructions at the PTX level. GOPTX establishes a merged control flow graph (CFG) from original kernels, enabling to interleaving of instructions that were sequentially executed by default and minimizing pipeline stalls on data hazards. We further propose a latency-aware instruction weaving algorithm for more efficient instruction scheduling and an adaptive code slicing method to enlarge the scheduling space. Experimental evaluation demonstrates that GOPTX achieves an average speedup of $\mathbf{1 1. 2 \%}$ over the baseline concurrent execution, with a maximum improvement of 23%. The hardware resource utilization statistics show significant enhancements in eligible warps per cycle and resource use. Zejia Lin 0001, Mengyue Xi, Zhongchun Zheng, Wenxuan Pan, Xianwei Zhang 0001, Yutong Lu |
DAC | 5 |
| 2025 | Adaptive sparse structure development with pruning and regeneration for spiking neural networks
Bing Han 0010, Wenxuan Pan, Yi Zeng 0001 |
Inf. Sci. | 3 |
| 2025 | Brain-Inspired Multiscale Evolutionary Neural Architecture Search for Deep Spiking Neural NetworksabstractSpiking neural networks (SNNs) have been widely applied not only for their advantages in energy efficiency with discrete signal processing but also for their natural suitability to integrate multiscale biological plasticity. However, most SNNs still adopt the structure of the well-established deep neural networks (DNNs), with few attempts at implementing automatic neural architecture search (NAS) for SNNs. The neural motifs topology, modular regional structures, and global cross-brain region connections in the human brain are the product of natural evolution, serving as a perfect reference for designing brain-inspired SNN architecture. Here, we propose an efficient multiscale evolutionary NAS (MSE-NAS) for SNN, simultaneously considering micro-, meso-, and macro-scale brain topologies as the evolutionary search space and is supplemented with customized brain-inspired indirect evaluation (BIE) function, encoding scheme and genetic operations. This is the first instance that the evolutionary characteristics of microconnections and electrophysiological patterns have been incorporated into one single evolutionary framework. The proposal of MSE-NAS proves that the evolutionary structure and mechanism of the human brain can essentially help better handle artificial intelligence tasks, revealing the important value and key role of integrating evolutionary computation (EC) principles in optimizing biologically realistic neural models. Extensive experiments demonstrate that MSE-NAS achieves superior performance with shorter simulation steps on static datasets (CIFAR10 and CIFAR100) and neuromorphic datasets (CIFAR10-DVS and DVS128-Gesture). More importantly, the emergence of general capabilities, such as transferability and robustness brought about by evolution confirms the innovative progress and important value of EC in the field of brain-inspired intelligence. Wenxuan Pan, Guobin Shen, Bing Han 0010, Yi Zeng 0001 |
IEEE Trans. Evol. Comput. | 1 |
| 2023 | Enhancing Efficient Continual Learning with Dynamic Structure Development of Spiking Neural NetworksabstractChildren possess the ability to learn multiple cognitive tasks sequentially, which is a major challenge toward the long-term goal of artificial general intelligence. Existing continual learning frameworks are usually applicable to Deep Neural Networks (DNNs) and lack the exploration on more brain-inspired, energy-efficient Spiking Neural Networks (SNNs). Drawing on continual learning mechanisms during child growth and development, we propose Dynamic Structure Development of Spiking Neural Networks (DSD-SNN) for efficient and adaptive continual learning. When learning a sequence of tasks, the DSD-SNN dynamically assigns and grows new neurons to new tasks and prunes redundant neurons, thereby increasing memory capacity and reducing computational overhead. In addition, the overlapping shared structure helps to quickly leverage all acquired knowledge to new tasks, empowering a single network capable of supporting multiple incremental tasks (without the separate sub-network mask for each task). We validate the effectiveness of the proposed model on multiple class incremental learning and task incremental learning benchmarks. Extensive experiments demonstrated that our model could significantly improve performance, learning speed and memory capacity, and reduce computational overhead. Besides, our DSD-SNN model achieves comparable performance with the DNNs-based methods, and significantly outperforms the state-of-the-art (SOTA) performance for existing SNNs-based continual learning methods. Bing Han 0010, Yi Zeng 0001, Wenxuan Pan, Guobin Shen |
IJCAI | 4 |