EDBT 2026 Demo / reviewers in the wild / expert
Mattia Tibaldi
dblp:293/7869
· DBLP profile ↗
4ranked-venue papers
2as first author
4since 2021 · last 2026
0000-0003-1113-3987ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 2 first-author · 4 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Artemis: Co-Simulation of Power Microgrids and Energy-Aware Cloud Data CentersabstractThe growing demand for power to support new cloud services raises the question of how to power future data center infrastructures. A power microgrid and cloud simulator that can act as a unified digital twin of these new infrastructures is crucial for studying emerging scenarios. In this article, we propose Artemis, a co-simulation environment for power microgrids and cloud data centers. Artemis extends the combination of the CloudSim Plus simulator and the Amethyst virtual machine allocation and migration policy with a generalized power microgrid model. Ultimately, Artemis enables the study of modular power microgrids with custom electrical policies and returns performance metrics and visualizations of the data center’s status under observation. Mattia Tibaldi, Sara Vinco, Christian Pilato |
DATE | 1 |
| 2024 | A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST ApproachabstractModern big data workflows are characterized by computationally intensive kernels. The simulated results are often combined with knowledge extracted from AI models to ultimately support decision-making. These energy-hungry workflows are increasingly executed in data centers with energy-efficient hard-ware accelerators since FPG As are well-suited for this task due to their inherent parallelism. We present the H2020 project EVEREST, which has developed a system development kit (SDK) to simplify the creation of FPGA-accelerated kernels and manage the execution at runtime through a virtualization environment. This paper describes the main components of the EVEREST SDK and the benefits that can be achieved in our use cases. Christian Pilato, Subhadeep Banik, Jakub Beránek, Fabien Brocheton, Jerónimo Castrillón, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi, Karl F. A. Friebel, Antonella Galizia, Matteo Grasso, Paulo Silva 0002, Jan Martinovic, Gianluca Palermo, Michele Paolino, Andrea Parodi, Antonio Parodi, Fabio Pintus, Raphael Polig, David Poulet, Francesco Regazzoni 0001, Burkhard Ringlein, Roberto Rocco, Katerina Slaninová, Tom Slooff, Stephanie Soldavini, Felix Suchert, Mattia Tibaldi, Beat Weiss, Christoph Hagleitner |
DATE | 29 |
| 2023 | Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid DynamicsabstractNumerical simulations can help solve complex problems. Most of these algorithms are massively parallel and thus good candidates for FPGA acceleration thanks to spatial parallelism. Modern FPGA devices can leverage high-bandwidth memory technologies, but when applications are memory-bound designers must craft advanced communication and memory architectures for efficient data movement and on-chip storage. This development process requires hardware design skills that are uncommon in domain-specific experts. In this paper, we propose an automated tool flow from a domain-specific language (DSL) for tensor expressions to generate massively-parallel accelerators on HBM-equipped FPGAs. Designers can use this flow to integrate and evaluate various compiler or hardware optimizations. We use computational fluid dynamics (CFD) as a paradigmatic example. Our flow starts from the high-level specification of tensor operations and combines an MLIR-based compiler with an in-house hardware generation flow to generate systems with parallel accelerators and a specialized memory architecture that moves data efficiently, aiming at fully exploiting the available CPU-FPGA bandwidth. We simulated applications with millions of elements, achieving up to 103 GFLOPS with one compute unit and custom precision when targeting a Xilinx Alveo U280. Our FPGA implementation is up to 25x more energy-efficient than expert-crafted Intel CPU implementations. Stephanie Soldavini, Karl F. A. Friebel, Mattia Tibaldi, Gerald Hempel, Jerónimo Castrillón, Christian Pilato |
ACM Trans. Reconfigurable Technol. Syst. | 3 |
| 2023 | A Survey of FPGA Optimization Methods for Data Center Energy EfficiencyabstractThis article provides a survey of academic literature about field programmable gate array (FPGA) and their utilization for energy efficiency acceleration in data centers. The goal is to critically present the existing FPGAs energy optimization techniques and discuss how they can be applied to such systems. To do so, the article explores current energy trends and their projection to the future with particular attention to the requirements set out by theEuropean Code of Conduct for Data Center Energy Efficiency. The article then proposes a complete analysis of over ten years of research in energy optimization techniques, classifying them by purpose, method of application, and impacts on the sources of consumption. Finally, we conclude with the challenges and possible innovations we expect for this sector. Mattia Tibaldi, Christian Pilato |
IEEE Trans. Sustain. Comput. | 1 |