Compressed-sensing (CS)-based channel estimation is a promising technology for future millimeter wave (mmWave) multiple-input–multiple-output (MIMO) systems, enabling significant pilot reduction and improved estimation accuracy. Channel estimators based on matching pursuit (MP) variants offer lower complexity compared with other CS algorithms, but suffer from high latency due to their iterative nature, hindering efficient hardware implementation. To mitigate this issue, this article introduces a turbo pursuit (TP) strategy that relaxes sequential dependencies in MP variants, enabling parallel processing and pipelined implementation. To demonstrate the effectiveness of TP, this article further introduces turbo implicit pursuit (TIP), a hardware-friendly instance of TP that leverages a prioritized gradient descent (GD) strategy for low-complexity least squares (LS) solving. A hardware auto-generator for TIP is then proposed using a formula representation approach, which constructs a parameterized hardware-algorithm design space and enables hardware-algorithm co-optimization. Our optimized$32 \times 4$TIP MIMO channel estimator ASIC in 65-nm CMOS achieves 0.53-$\mu $s latency under 18.75% measurements. Compared with prior implementations of MP variants, this work achieves higher or comparable estimation accuracy with over 18% latency reduction and over 5$\times$higher throughput to area ratio (TAR) for ASICs, and over 90% latency reduction with over 3$\times$higher hardware efficiency for FPGAs.

In comparison to 4G, 5G wireless needs to support a broader range of applications. Therefore, both low-density parity-check (LDPC) codes and polar codes have been standardized by 5G new radio (NR) to fulfill the requirements of data channel and control channel, respectively. Usually, LDPC/polar decodings are implemented by separate hardware, leading to low area efficiency. Though decoders which can handle both codes have been proposed, how to compromise between throughput and efficiency has always been a persistent dilemma due to the absence of a unified and smooth integration methodology. To this end, by fully utilizing the common parts of graph-theoretic algorithms for both codes, this paper presents a unified decoder (UniDec) which is fully compatible with 5G NR LDPC/polar codes. This UniDec enables three key approaches:1) unified processing nodes for both codes,2) configurable permutation networks with multi-parallelism, and3) flexible scheduling for 5G NR parameter configuration, guaranteeing both high data throughput and area efficiency. Implemented in 40nm CMOS, the UniDec attains a maximum of$33.64\times $throughput and$5.98\times $area efficiency compared to its multi-mode counterparts. Even compared with the state-of-the-art (SOA) dedicated ones, the UniDec still maintains a competitive edge in terms of throughput, energy, and area efficiency. It is noted that this methodology can be generalized to other factor-graph based signal processing algorithms.

Thanks to its near-optimal performance, breadth-first search detection (BFSD) finds widespread application in small-scale MIMO systems. However, existing BFSD methods struggle to effectively configure the width (number of candidate nodes) for each layer, resulting in prohibitive complexity in large-scale MIMO systems. To address this, we propose two width optimization schemes for BFSD. We introduce a layer-by-layer optimization framework to reduce the design space of width configurations, and a Monte Carlo-assisted method to link width configurations to detection performance. Using this linking scheme in the reduced design space, we formulate the first width optimization scheme given specific performance constraints. Then, we present another scheme that employs a theoretical linking method as an alternative to the Monte Carlo approach. Although slightly less effective, the second scheme has negligible complexity for width optimization, making it well-suited for communication scenarios with time-varying characteristics. In 128×128 MIMO systems, numerical results demonstrate that the optimized BFSD using our first and second schemes can reduce complexity by up to 82% and 65%, respectively, while achieving superior detection performance compared to state-of-the-art BFSD.

Soft-output decoder is of great importance to be applied in iterative receivers, of which belief propagation (BP) algorithm has been widely studied for 5G low-density parity- check (LDPC) and polar codes. However, for polar codes, BP decoding suffers from high computational complexity and unsatisfactory convergence. To this end, soft cancellation (SCAN) polar decoder has recently drawn attention from academia and can be further improved by using the bit-flipping strategy. Limited by the serial nature of message propagation, the SCAN flip (SCANF) decoder cannot meet a high throughput. In this paper, we accelerate the decoding speed by the fast processing mechanism, conducting Fast-SCANF decoder. The corresponding hardware architecture is designed with memory optimization and implemented by TSMC 40nm technology, delivering a 2.1 Gbps throughput and 65 pJ/b energy. To the knowledge of authors, this is the first SCANF hardware decoder.