In this work, a 3.5 GS/s voltage-controlled oscillator (VCO) analog-to-digital converter (ADC) using multi-stage noise shaping (MASH) is presented. This 28nm CMOS ADC achieves second-order noise shaping in an easily-scalable, open-loop configuration. A key enabler of the high-bandwidth MASH VCO ADC is the use of a multi-bit estimated error signal. With an OSR of 16, an SNDR of 67 dB and DR of 68 dB are achieved in 109.375 MHz bandwidth. The full-custom pseudo-analog circuits consume 9 mW, while the automatically generated digital circuits consume another 24 mW. A$\mathbf {FoM_{DR} = 163}$dB and core area of$\mathbf {0.017\,\mathbf {mm}^{2}}$are obtained.

In this work, we focus on the Power Supply Rejection and Common Mode Rejection performance of inverter based ring oscillators intended for use in VCO ADCs. We show that they are closely related to the circuit’s mismatch behavior of which we perform a systematic analysis. To this end, we construct a theoretical mismatch model for these ring oscillators, based on Pelgrom’s mismatch model. In addition, we generalize this model to include the mismatch in a generic tuning circuit. In this broad analysis, we show that, next to the obvious transistor size dependence, the mismatch is inversely proportional to the number of stages and hence, in theory, can always be suppressed up to the desired level in a VCO ADC, provided that the tune circuit is sized adequately. Furthermore, we demonstrate that the mismatch is dependent on the biasing of the ring, which becomes even more apparent when taking into account the influence of a tuning circuit. More specifically, strong inversion is almost always better than weak inversion, and current control is preferred over voltage control. Finally, we perform extensive Monte Carlo simulations, with a commercially available 65nm CMOS process, which match our analytical predictions nearly perfectly.

Recently a study of the analog behavior of ring oscillators was presented from the perspective of VCO ADC design [1]. In this study it was shown that the electrical behavior between the two tuning terminals of such a ring oscillator can be modeled by a diode element. The VCO (phase-)noise can be modeled as an equivalent input-referred noise voltage source in series with this diode. Unfortunately, it was found that this input-referred noise was dependent on the driving impedance. In the prior study only ideal voltage and ideal current control were elaborated. In this work, we generalize the VCO noise model for an arbitrary driving impedance. This enables the noise optimization of a VCO with an arbitrary driving circuit which was not possible with the prior theory. In this work we present such a noise optimization for the linearizing resistive VCO drive circuit of [2], [3]. We show that for this circuit the biasing of the ring is rather uncritical, which is in strong contrast with the result for a pure voltage mode drive circuit, where the biasing of the ring has a major impact on the noise performance.

For the design of ring oscillator-based ADCs, little has been reported on how to optimally co-design the readout scheme and the ring oscillator core towards optimal energy efficiency. This paper describes a methodology to find this optimum for a target SQNR and signal bandwidth, for the case of 1st-order quantization noise shaping. In short, starting from initial assumptions on the VCO, the readout optimization boils down to finding the best VCO frequency. From this, the number of readout phases, the sampling frequency of the readout and the number of bits in the quantizers are derived. Then, it is explained how to adjust the VCO core toward the corresponding optimal VCO configuration. This is discussed for the case of a current-controlled ring oscillator, indicating the main constraints that define the design space for such a VCO optimization. If the actual VCO configuration is bounded by practical constraints, this approach can be re-iterated where a new readout optimization is performed taking these constraints into account.

In this work, we focus on the three most relevant pseudo-digital ring oscillator circuits for VCO A/D conversion. First, we show that they can be accurately modeled by an equivalent 2-terminal diode-like element. Next, we study the main analog performance figures: the effective oscillation frequency (which affects the quantization noise of a VCO ADC), the input referred noise and the power efficiency both for voltage and current control. We do this both through theoretical modeling as well as through simulations, which are in good agreement with each other. Our study highlights several important independencies: e.g. most performance metrics are independent on the number of VCO stages and the external load capacitance on the VCO nodes. In contrast to these independencies, we identify several important dependencies. In particular, we show that the biasing of the ring has an enormous impact on power efficiency of the ring. This dependency is different for the case of a voltage- or current mode configuration of the ring.