Circuits based on tunneling FET (TFET) devices are fueling the beyond CMOS logic design, meeting the ultra-low-power demands for Internet-of-Things (IoT) applications. This paper presents a highly energy-efficient hybrid TFET/FinFET level shifter (LS) circuit, providing a robust signal up-conversion from deep subthreshold voltage. A pulse-triggered dynamic fully-regenerative latch and two modified dynamic current generators are incorporated to overcome the timing variation of input differential signals and current contention in the cross-coupled circuit. The simulation results show that the hybrid TFET/FinFET LS circuit has achieved a low propagation delay, dynamic power consumption, and power-delay-product (PDP) of ≤378 ps, ≤39.6 μW, and ≤13,950 ns-nW, respectively while converting the input signal from the ultra-low-voltage of sub-50mV to the nominal supply voltage of FinFET (0.8-1.2V). The proposed architecture has achieved up to 2.71-to-15.99x improvement in PDP compared to the reported state-of-the-art LS architectures.

With Moore's law reaching its limits, the use of new materials or new devices' structure has emerged as the next generation of CMOS devices. Among all, tunneling field-effect transistors (TFETs) have achieved a steep sub-threshold slope of less than 60mV/decade yet there is a lack of a complete process design kit (PDK) for large-scale circuit design. Hence, we present an open-source 15nm TFET PDK (15nmTFETPDK), which is based on FreePDK15 with additional support for open-source TFET models and its associated Cadence Virtuoso pcell in OA format and Mentor Calibre physical verification files. Our users can design their circuit in the Cadence Virtuoso platform and verify the consistency of the drawn layout and the circuit through the Calibre Platform. We hope that this open-source PDK allows them to further advance their research with new emerging devices.

Level converting is increasingly difficult in ultra-low voltage circuits with the aggressive scaling down of the input voltage. In this paper, we proposed a wide output range level shifter (LS) with the ultra-low input voltage. The proposed LS is integrated with a positive flip-flop function with a three-phase time borrowing scheme at the sampling edge. The working principle eliminates the current contention problem in the conventional cross-coupled level shifters, which allows a much higher output range at ultra-low input. The time borrowing technique also allows a relaxed timing constraint, which increases the timing margin and improves robustness against variation in ultra-low voltage circuits. The proposed LS is implemented with 45nm CMOS technology. Simulation results show that the proposed structure achieves a propagation delay of 10.01ns, power consumption of 11.23pW, and a power-delay-product (PDP) of 112,412ns-nW when converting an input signal of 200mV to an output level of 3 V.