EDBT 2026 Demo / reviewers in the wild / expert
Claudio Montanari
dblp:295/3187
· DBLP profile ↗
1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Operating systems · 50% Compilers and program optimization · 50% | |
| Computer networks
1 paper |
Datacenter networks · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 100% |
Topics — the 2 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › program instrumentation
compiler instrumentation |
0.5 | 1 | 2021 | Frequent background polling on a shared thread, using light-weight compiler interrupts · PLDI 2021 |
Parallel and multicore computing › parallel scheduling
thread scheduling |
0.1 | 1 | 2021 | Frequent background polling on a shared thread, using light-weight compiler interrupts · PLDI 2021 |
Methods — techniques the papers use, named apart from their topics
compiler instrumentation · 1.5
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2021 | Frequent background polling on a shared thread, using light-weight compiler interruptsabstractRecent work in networking, storage and multi-threading has demonstrated improved performance and scalability by replacing kernel-mode interrupts with high-rate user-space polling. Typically, such polling is performed by a dedicated core. Compiler Interrupts (CIs) instead enable efficient, automatic high-rate polling on a shared thread, which performs other work between polls. CIs are instrumentation-based and light-weight, allowing frequent interrupts with little performance impact. For example, when targeting a 5,000 cycle interval, the median overhead of our fastest CI design is 4% vs. 800% for hardware interrupts, across programs in the SPLASH-2, Phoenix and Parsec benchmark suites running with 32 threads. We evaluate CIs on three systems-level applications: (a) kernel bypass networking with mTCP, (b) joint kernel bypass networking and CPU scheduling with Shenango, and (c) delegation, a message-passing alternative to locking, with FFWD. For each application, we find that CIs offer compelling qualitative and quantitative improvements over the current state of the art. For example, CI-based mTCP achieves ≈2× stock mTCP throughput on a sample HTTP application. Nilanjana Basu, Claudio Montanari, Jakob Eriksson |
PLDI | 2 |