Logic Locking aims to hide the original functionality of the design using a secret key. It protects hardware intellectual properties (IPs) against IP piracy or IC overproduction. However, an attacker analyzes the structural traces and/or uses Boolean satisfiability based technique called SAT attack to break such logic locking schemes. This motivates us to find a logic locking technique that can work against both SAT and structural analysis attacks. Therefore, this paper introduces a novel multiplier-based logic locking scheme. Leveraging the inherent complexity of multiplier circuits, the proposed scheme exponentially increases the time required for each iteration of a SAT attack. Moreover, a heuristic is also proposed to identify appropriate locations for inserting multiplier instances to increase the number of iterations. The multiplier-based logic locking scheme is further combined with the Anti-SAT scheme to create a robust and effective defense mechanism against SAT attacks and the various other attacks exploiting structural traces. The proposed technique is resilient to the state-of-the-art attack dedicated to the existing compound logic locking schemes. Moreover, the proposed compound logic locking scheme, requires half the number of key inputs than the state-of-the-art logic locking scheme while providing the similar level of security.

Today's general-purpose graphics processing units (GPGPUs) offer phenomenal performance to applications from a variety of fields. Despite its memory-latency tolerant parallel architecture, GPGPU cores do not attain optimal performance with most of the memory-intensive applications which add a significant load on memory-resources. The existing thread scheduling mechanism is not optimized to address this challenge for latency-sensitive applications. In this paper, we propose a warp-scheduling policy that defers the execution of all those warps which will potentially cause long-latency memory-stalls, to prevent the resulting congestion in interconnect network and DRAM bandwidth. The proposed policy uses a predictor in each core of the GPU to predict whether or not the data can be retrieved from the L1-cache at the time of increased congestion to effectively reduce the number of warps that can be paused and keep the cores active. This translates to an average performance improvement of 11.6% and up to 41.2% over the state-of-the-art scheduling policies across a diverse selection of applications with a 4.2% increase in average power consumption.

Massively parallel processors such as graphics processing units (GPUs) often face the challenge of resource underutilization due to varying resource proclivity of workloads. Running multiple applications on a GPU has been an efficient and known alternative to mitigate underutilization. This paper proposes a multi-application oriented framework that carries out dynamic optimizations based on the operational intensities of various applications. Our framework analyzes applications based on operational intensities to identify their bottleneck resources using Roofline model. We demonstrate that the proposed optimizations improve the utilization and system-wide throughput of the GPU co-running applications with irregular resource demands. The dynamic optimizations improve the performance by 14.8% on average and up to 72.4% over a state-of-the-art spatial multitasking technique.