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Xiaoqiao Mu

dblp:295/5946 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 50% Integrated circuit design · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design		 0.512021
A Formal Proof of PG Recurrence Equations of Parallel Adders · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
Electronic design automation › hardware verification and test
formal verification		 0.512021
A Formal Proof of PG Recurrence Equations of Parallel Adders · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
Electronic design automation
hardware verification and test		 0.512021
A Formal Proof of PG Recurrence Equations of Parallel Adders · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021
Integrated circuit design › digital arithmetic circuits › parallel adder
parallel prefix adder		 0.512021
A Formal Proof of PG Recurrence Equations of Parallel Adders · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2021

Methods — techniques the papers use, named apart from their topics

recurrence equations · 0.5formal proof · 0.5
YearPublicationVenuePosition
2021 A Formal Proof of PG Recurrence Equations of Parallel Adders
abstract
Parallel adders are extensively used in high-performance computer design and hardware acceleration for large-scale data processing. In the adder design theory, a key property of the group propagated carry and the group generated carry is based on the two recurrence equations. The property is fundamental to many parallel prefix adders. However, there is no proof of the property in the literature. This article presents a rigorous and complete proof for it. The proof can leverage a solid ground for a formal verification methodology for parallel adder-based chip design.
Guowu Yang, Xiaoqiao Mu, Yongqian Fan
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.5