Analog Computing-In-Memory (ACiM) accelerators with multi-level cells (MLCs) offer high density and area benefits for DNNs. To enhance efficiency, ADC resolution needs to be minimized, but this introduces significant quantization errors, lowering accuracy. Additionally, device noise and ADC integral nonlinearity (INL) noise further degrade accuracy. To address these challenges, we propose a training method that reduces ADC resolution while compensating for noise generated in ACiM arrays. By incorporating pseudo-quantization noise into Partial-Sum Training (PST), our approach not only stabilizes PST but also trains the model to become robust to ACiM-specific noise effects. Experimental results based on an industry ReRAM technology show that our PST scheme demonstrates robust noise tolerance across various ACiM configurations and maintains accuracy degradation within 1% even in the presence of cell conductance variability and ADC INL noise, while enabling low-resolution ADCs that reduces area and energy consumption by up to 16× and 31×, respectively.

Logic compatible eDRAM cell-based computing-in-memory (CIM) neural network accelerators have been actively studied as an energy-efficient neural network computing platform thanks to their small cell size and low static power compared to SRAM. However, previous eDRAM-based CIM accelerators suffer from significant accuracy degradation caused by process, voltage, temperature (PVT) variations and short retention time. To overcome the issues, we introduce a PVT-variation tolerant capacitive coupling-based eDRAM cell that has a much longer retention time than previous works. Simulation results show that the proposed eDRAM cell has up to 50× higher retention time compared to the state-of-the-art designs.

Recently, various in-memory computing accelerators for low precision neural networks have been proposed. While in-memory Binary Neural Network (BNN) accelerators achieved significant energy efficiency, BNNs show severe accuracy degradation compared to their full precision counterpart models. To mitigate the problem, we propose TAIM, an in-memory computing hardware that can support ternary activation with negligible hardware overhead. In TAIM, a 6T SRAM cell can compute the multiplication between ternary activation and binary weight. Since the 6T SRAM cell consumes no energy when the input activation is 0, the proposed TAIM hardware can achieve even higher energy efficiency compared to BNN case by exploiting input 0's. We fabricated the proposed TAIM hardware in 28nm CMOS process and evaluated the energy efficiency on various image classification benchmarks. The experimental results show that the proposed TAIM hardware can achieve ~ 3.61× higher energy efficiency on average compared to previous designs which support ternary activation.