Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) has emerged as a compelling candidate for embedded memory due to its non-volatility, high endurance, and low power consumption. However, manufacturing process limitations result in low tunnel magnetoresistance ratios (TMR), leading to narrow read windows. Therefore, high-performance trimming is required, yet existing self-trimming schemes face challenges in balancing trimming time, accuracy, and flexibility. To address these issues, this paper proposes a Dynamic Stepsize Single-write Pattern Trimming (DSPT) algorithm that uses dynamic step sizes and a single-write pattern to rapidly lock the read window boundary range, followed by binary search for precise boundary determination, thereby reducing trimming time while maintaining high accuracy. A parallel variant, DSPT_P, is further proposed, allowing each sense amplifier (SA) to shift gears independently in advance and introducing an Address Reliability Limit (ARL) for result assessment. Finally, a BuiltIn Self-Test (BIST) architecture is proposed to implement the proposed trimming schemes.