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Sergi Laut

dblp:295/9320 · DBLP profile ↗
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3ranked-venue papers
3as first author
3since 2021 · last 2024
0000-0002-8727-0518ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-author · 3 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
High-performance computing · 85% GPUs and heterogeneous computing · 9% Memory systems · 4%

Topics — the 10 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing
numerical linear algebra
1.832024
Extending Sparse Patterns to Improve Inverse Preconditioning on GPU Architectures · HPDC 2024
Communication-aware Sparse Patterns for the Factorized Approximate Inverse Preconditioner · HPDC 2022
Cache-aware Sparse Patterns for the Factorized Sparse Approximate Inverse Preconditioner · HPDC 2021
High-performance computing › numerical linear algebra
preconditioner
1.832024
Extending Sparse Patterns to Improve Inverse Preconditioning on GPU Architectures · HPDC 2024
Communication-aware Sparse Patterns for the Factorized Approximate Inverse Preconditioner · HPDC 2022
Cache-aware Sparse Patterns for the Factorized Sparse Approximate Inverse Preconditioner · HPDC 2021
High-performance computing › numerical linear algebra › preconditioner
sparse approximate inverse
1.832024
Extending Sparse Patterns to Improve Inverse Preconditioning on GPU Architectures · HPDC 2024
Communication-aware Sparse Patterns for the Factorized Approximate Inverse Preconditioner · HPDC 2022
Cache-aware Sparse Patterns for the Factorized Sparse Approximate Inverse Preconditioner · HPDC 2021
GPUs and heterogeneous computing
GPU computing
0.812024
Extending Sparse Patterns to Improve Inverse Preconditioning on GPU Architectures · HPDC 2024
High-performance computing
distributed memory systems
0.612022
Communication-aware Sparse Patterns for the Factorized Approximate Inverse Preconditioner · HPDC 2022
High-performance computing › sparse linear algebra › sparse matrix computation
sparse matrix-vector multiplication
0.512021
Cache-aware Sparse Patterns for the Factorized Sparse Approximate Inverse Preconditioner · HPDC 2021
High-performance computing › iterative methods
conjugate gradient
0.212024
Extending Sparse Patterns to Improve Inverse Preconditioning on GPU Architectures · HPDC 2024
Parallel and multicore computing
load balancing
0.212022
Communication-aware Sparse Patterns for the Factorized Approximate Inverse Preconditioner · HPDC 2022
Memory systems › cache
cache behavior
0.112021
Cache-aware Sparse Patterns for the Factorized Sparse Approximate Inverse Preconditioner · HPDC 2021
Memory systems › cache
cache miss reduction
0.112021
Cache-aware Sparse Patterns for the Factorized Sparse Approximate Inverse Preconditioner · HPDC 2021

Methods — techniques the papers use, named apart from their topics

sparse pattern extension · 0.8filtering strategy · 0.6communication-aware pattern extension · 0.6cache-aware pattern extension · 0.5
YearPublicationVenuePosition
2024 Extending Sparse Patterns to Improve Inverse Preconditioning on GPU Architectures
abstract
Graphic Processing Units (GPUs) have become a key component of high-end computing infrastructures due to their massively parallel architecture, which delivers large floating-point operations per cycle rates. Many scientific workloads benefit from GPUs and, in particular, numerical methods solving linear systems of equations Ax = b typically run on GPUs. Among them, the Conjugate Gradient (CG) method, which targets linear systems with Symmetric and Positive Definite (SPD) matrices, runs on GPUs using its preconditioned form. However, state-of-the-art preconditioning techniques like the Factorized Sparse Approximate Inverse (FSAI) preconditioner ignore the benefits of data coalescence and locality on GPU architectures and leave substantial performance on the table. These approaches are exclusively based on numerical criteria.
Sergi Laut, Ricard Borrell, Marc Casas
HPDC1
2022 Communication-aware Sparse Patterns for the Factorized Approximate Inverse Preconditioner
abstract
The Conjugate Gradient (CG) method is an iterative solver targeting linear systems of equations Ax=b where A is a symmetric and positive definite matrix. CG convergence properties improve when preconditioning is applied to reduce the condition number of matrix A. While many different options can be found in the literature, the Factorized Sparse Approximate Inverse (FSAI) preconditioner constitutes a highly parallel option based on approximating A-1. This paper proposes the Communication-aware Factorized Sparse Approximate Inverse preconditioner (FSAIE-Comm), a method to generate extensions of the FSAI sparse pattern that are not only cache friendly, but also avoid increasing communication costs in distributed memory systems. We also propose a filtering strategy to reduce inter-process imbalance. We evaluate FSAIE-Comm on a heterogeneous set of 39 matrices achieving an average solution time decrease of 17.98%, 26.44% and 16.74% on three different architectures, respectively, Intel Skylake, Fujitsu A64FX and AMD Zen 2 with respect to FSAI. In addition, we consider a set of 8 large matrices running on up to 32,768 CPU cores, and we achieve an average solution time decrease of 12.59%.
Sergi Laut, Marc Casas, Ricard Borrell
HPDC1
2021 Cache-aware Sparse Patterns for the Factorized Sparse Approximate Inverse Preconditioner
abstract
Conjugate Gradient is a widely used iterative method to solve linear systems Ax=b with matrix A being symmetric and positive definite. Part of its effectiveness relies on finding a suitable preconditioner that accelerates its convergence. Factorized Sparse Approximate Inverse (FSAI) preconditioners are a prominent and easily parallelizable option. An essential element of a FSAI preconditioner is the definition of its sparse pattern, which constraints the approximation of the inverse A-1. This definition is generally based on numerical criteria. In this paper we introduce complementary architecture-aware criteria to increase the numerical effectiveness of the preconditioner without incurring in significant performance costs. In particular, we define cache-aware pattern extensions that do not trigger additional cache misses when accessing vector x in the y=Ax Sparse Matrix-Vector (SpMV) kernel. As a result, we obtain very significant reductions in terms of average solution time ranging between 12.94% and 22.85% on three different architectures - Intel Skylake, POWER9 and A64FX - over a set of 72 test matrices.
Sergi Laut, Ricard Borrell, Marc Casas
HPDC1