Memristor-based computation-in-memory (CiM) architectures address the growing computational demands of AI accelerators by enabling analog matrix-vector multiplication (MVM) directly within the memory array. Passive (selectorless) memristive crossbars are particularly attractive for such architectures due to their high density and compatibility with back-end-of-line fabrication. Here, AI model parameters are stored as memristor conductances, and MVM is performed in situ by activating multiple rows simultaneously and sensing the resulting column currents. As a result, column currents become the primary observable, making column-level fault detection more relevant for AI workloads than conventional March-based cell-level tests, which are specially time - and energy-intensive for passive crossbars due to specialized biasing methods. To address this, we propose a current-based testing methodology tailored to passive crossbars that detects and diagnoses faulty columns while accounting for non-idealities such as sneak-path currents, line resistance, and process variations. Faulty columns are detected by programming all cells to a uniform state and measuring column-current deviations, followed by targeted test patterns to estimate per-column fault density. On a $64 \times 64$ array, the proposed approach achieves 100% faulty column detection, 98% overall fault coverage, and a $2.3 \times$ speed-up in test time compared to conventional March tests. Hence, providing a fast and efficient solution for manufacturing screening of passive crossbars with sufficient diagnostic resolution to support systemlevel fault tolerance for AI applications.

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising alternative to existing memory technologies. However, STT-MRAM faces reliability challenges, primarily due to stochastic switching, process variation, and manufacturing defects. These reliability challenges become even worse due to interconnect parasitic resistive-capacitive effects, potentially compromising the reliability of memory cells located far from the write driver. This can severely impair the manu-facturing yield and large-scale industrial adoption. Toaddressthis, we propose an interconnect-aware error correction coding (InterA-ECC), which provides non-uniform error correction to a different zone of the memory subarray. The proposed InterA-ECC strategy selectively applies robust error-correction code (ECC) to specific rows within the subarray rather than uniformly across all rows, reducing ECC parity bits while enhancing bit error rate resiliency in the most vulnerable memory zone.

Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising alternative to conventional CMOS memory technologies for on-chip cache replacement. Due to its superior access speeds, high endurance, and scalability, it is being extensively considered a promising candidate for last-level cache replacement. This technology has reached considerable industrial maturity, with several foundries now offering this emerging technology. Despite its advantages, STT-MRAM faces reliability challenges, primarily due to its asymmetric error characteristics during write and read operations, where the likelihood of a bit transitioning from$1\rightarrow 0$differs from that of$0\rightarrow 1$. Conventional Error Correcting Codes (ECCs) do not account for such asymmetry between these bit-flip types and fall short of providing balanced error correction. This article introduces an efficient asymmetric and adaptive error correction in STT-MRAM based on the Hamming weight of data bits that operates with negligible overhead alongside a standard ECC framework. Our simulation findings indicate that the proposed technique offers substantial enhancement in reliability, measured by a cache word/block error rate, tested across the last level cache data for various SPEC CPU2017 benchmarks. This enhancement in reliability is achieved without inserting excessive memory and hardware overhead, and without impacting system performance, presenting a compelling case for enhancing the operational reliability of STT-MRAM.

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising alternative to existing CMOS memory technologies due to its non-volatility, fast read access, and scalability potential. This has reached the level of industrial maturity as several foundries now offer this technology. However, it is sensitive to various failure mechanisms, such as manufacturing defects in both CMOS and magnetic layers, temperature variation, repetitive writes, and oxide breakdown, which can cause early cell failure leading to hard errors. This can severely impair the manufacturing yield and its large-scale industrial adoption. To ensure high manufacturing yield and infield reliability, we propose a new block error correction pointer (BECP) as a hard error correction technique for STT-MRAM. The proposed method divides large word lengths into smaller sub-blocks and assigns a specific base value per sub-block to determine the offset location of the hard error. This allows storing only the offset value instead of the absolute address of the hard error for each sub-block. The results depict that the proposed method is storage efficient and has low decoding complexity compared to the existing state-of-the-art methods. We incorporate experimental measurement data obtained from manufactured STT-MRAM chips at different die locations to get the hard error distribution. The proposed method aligns well with our specific STT-MRAM error distribution measurements.

Neural networks (NNs) have shown outstanding performance in various domains, leading to widespread deployment on various hardware devices. They require large memories to store the NN weight parameters, which are susceptible to numerous permanent and transient faults. Therefore, error detection and correction mechanisms with certain guarantees should be provided to ensure reliable NN operation, especially in safety-critical applications. Error Correction Codes (ECCs) are a common approach to protecting memories against these failures, but they impose significant memory overheads. This work proposes NN-ECC, a multi-task learning objective that integrates linear block ECC into the NN parameters during training. The proposed NN-ECC does not increase the total number of NN parameters and eliminates all storage requirements for parity bits of different ECCs. Unlike existing methods, which selectively eliminate the storage overhead with limited error correction and necessitate specific weight distributions to utilize redundant weight bits for ECC parity, our approach is versatile and can accommodate various ECC schemes with different correction capabilities without imposing constraints on weight distributions. Moreover, the proposed NN-ECC does not deteriorate the baseline accuracy due to ECC encoding.

The matrix-vector multiplication (MVM) is one of the most frequent operations performed in deep learning hardware accelerators. The crossbar array structure with memristive devices as a building block has an inherent capability to perform energy-efficient MVM. However, the memristive devices suffer from various non-idealities as well as limited number of stable levels. Therefore, the reliability and in turn inference accuracy of the deep learning application is negatively impacted. Thus, this paper presents a low overhead checksum-based error correction method for memristive crossbars for MVM computation. The proposed methodology alleviates the problem of storing the checksum value into multiple columns of the crossbar due to the limited number of stable levels of memristive devices. The number of extra columns required for storing the checksum value is reduced, resulting in a significant reduction in the memory overhead by up to 75%. The proposed method scales the checksum value of trained neural networks (NNs) and then performs checksum-aware retraining, and results show negligible impact (∼3%) on the inference accuracy of the NNs on MNIST, Fashion-MNIST, CIFAR-10, and Veg-15 datasets.

Matrix-vector multiplication (MVM) is one of the most frequent operations performed in deep learning and big data applications. On the other hand, the Memory wall problem in traditional processor-centric architectures limits the performance of these applications. The crossbar array of emerging non-volatile memristive devices (memristive crossbar) provides an energy-efficient hardware implementation of MVM for deep learning accelerators and edge computing hardware. However, non-idealities as well as manufacturing and runtime defects of the memristive devices may severely impact the reliability of target applications. This paper presents a new online block error correction technique for memristive crossbars. It enables reliable MVM computation by combining the idea of checksum and Hamming code-based linear coding scheme. The proposed method can correct any number of errors in one particular array block containing multiple columns. An adaptive error correction coding strategy is also presented, so that the ratio of data columns to the parity checksum columns can be adjusted at runtime based on the fault rate, enabling the optimum use of data and parity checksum columns.

This paper discusses a discrete optimization problem of optimal design of Power Delivery Networks (PDN) in VLSI systems. In this paper, a practical case study is presented, where, in order to design an efficient PDN, the cumulative impedance of the PDN is optimized below the target impedance. For this purpose, the decoupling capacitors (from commercially available capacitors) are chosen in such a way that the minimum number of the capacitors are used, and also their optimal locations are identified. The different variants of inertia weight strategies incorporated into particle swarm optimization algorithms are used for this purpose. A comparative analysis of the performance of these algorithms is also presented.