Compact models of transistors are essential for simulating and optimizing circuits with the use of SPICE simulation tool. Parameter extraction, which is calibrating these models, is essential to ensure their alignment with measured or simulated data. However, conventional parameter extraction methods are generally iterative and experience-dependent, requiring significant time and effort from modeling engineers. Moreover, as semiconductor devices and compact models become increasingly advanced, the need for a tailored extraction process for each model has become increasingly inefficient. To address the above challenges, this work proposes an agile transistor compact modeling framework, ATMAD. The proposed framework takes a compact model file and a set of electrical characteristic data as inputs, producing a calibrated model with minimal human intervention. ATMAD automatically retrieves the equations in the compact model and converts them into computational flow graphs, thus supporting different compact models with a generalized process. A graph unlooping technique is proposed to support automatic differentiation for compact models with implicit functions (e.g., series resistance and surface potential solving). Based on the computational flow graph, ATMAD adopts automatic differentiation technique to achieve automatic and parallel optimization of model parameters. The proposed ATMAD framework is validated on commonly-used compact models in academia and industry, showing its effectiveness for compact modeling for both I-V and C-V characteristics.

A 14GHz CML-based phase interpolator (PI) is proposed for a 4-way time-interleaved 56Gbaud clock and data recovery (CDR). The phase interpolator has a resolution of 7 bits and is implemented in 28 nm CMOS technology with a 1.0V power supply. The proposed PI consists of a PI controller, a slew-rate-control buffer, and a phase mixer. The distribution of the tail current sources, short-channel effect, and the slew rate of the input signals are analyzed and several methods are proposed to optimize the interpolation linearity. The measured integral non-linearity (INL) and the calculated differential non-linearity (DNL) are less than 1.20 LSB and 0.27 LSB respectively at 14GHz. The total power consumption is 8.48mW.

A 25Gb/s PAM-4 receiver is presented with 4- tap adaptive DFE and sampling clock optimization. PAM-4 signaling suffers more from non-optimal sampling clock phase which degrades BER. By finding the point with the least pre-cursor ISI, the sampling clock can be recovered with optimal phase, which improves the BER by as much as 109through 12.5dB channel loss. A novel clocked amplifier is implemented as a slicer to reduce the loop delay and meet the timing constraints of the direct feedback. Fabricated in 55nm CMOS technology, the receiver occupies 0.27mm2and consumes 185mW at 25Gb/s with a power supply of 1.2V.

A novel structure of analog signal processing circuits for coherent receivers is proposed and implemented in 28-nm CMOS technology with 1V supply voltage in this work. To avoid excessive taps in equalizer or prolix circuit modules, the system combines the crosstalk equalizer and carrier phase recovery circuits with the application of 2 kinds of multipliers to compensate linearity for higher accuracy. In order to achieve stronger converging ability, simplify the system realization and further reduce power dissipation, the chromatic dispersion equalizer uses DFE instead of FFE to eliminate post cursor. Simulation results show circuits are capable of equalizing signals of 40-ps/nm chromatic dispersion effect, 300-kHz dynamic polarization crosstalk and 100MHz frequency offset with power of 1.2 Watt.