Often, data stored in memory must be protected from naturally occurring and malicious errors. Methods for constructing codes that are robust with respect to errors injected into the data as well as into the address (in which the data are to be stored) are described. Several ways of extending data-protecting codes to address-and-data protecting codes are presented, and a generalization of the concepts behind CPCs – low cost codes for which no error injected into the data is ever completely masked – is given. A fundamental difference between attacks on the address and data and attacks that only target the data is detailed, and the consequences of this fundamental difference are briefly considered.

A hardware-based control flow monitoring technique enables the detection of errors in both the control flow and the instruction stream executed on a processor. However, as shown in recent publications, these techniques fail to detect malicious carefully-tuned manipulations of the instruction stream in a basic block. This article presents a non-linear encoder and checker that can cope with this weakness. It is a MAC based control flow checker that has the advantage of working with basic blocks of variable length, can detect every error, and performs the computation in real-time. The architecture can easily be modified to support different signature size and error masking probabilities.

Compact protection codes (CPCs) provide optimal protection against fault injections attacks on memory arrays content. Nevertheless, CPCs fail to detect errors injected into the address itself. Consequently, an adversary can write a correct data word to an erroneous address without being detected. This paper presents an efficient code, dubbed AD-CPC, which detects both data manipulations and faults injected into the address decoder. No additional redundancy bits are required and no latency is introduced. In addition, the new encoding has a negligible effect on the error masking probability of the original CPC. We provide theoretical bounds and experimental results that support these claims. We show that with r additional redundant bits every error can be detected with probability of at least 1 - 3.2-r.