EDBT 2026 Demo / reviewers in the wild / expert
Sohyeon Kim
dblp:296/0927
· DBLP profile ↗
4ranked-venue papers
1as first author
4since 2021 · last 2025
0000-0002-5443-386XORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-author · 4 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | High-throughput Point-Cloud Accelerator with Sparsity-aware Hierarchical Neighbor Voxel Search and SkippingabstractPoint cloud-based 3D sparse convolution networks are widely employed to process voxel features efficiently. However, the irregularity of voxel sparsity poses significant challenges, leading to increased hardware complexity and inefficiencies. We propose an algorithm-hardware co-design for sparse 3D convolution. At the algorithm level, an on-the-fly thresholdbased voxel skipping is adopted, enhancing efficiency. At the hardware level, a hierarchical 3-stage Voxel Search and Skipping is developed to systematically narrow down the non-zero search space, enhancing both performance and hardware utilization. We implemented the proposed accelerator in a 65 nm process to demonstrate a 77.7% reduction in delay compared to a baseline design, which does not support the proposed sparsity adaptations. The proposed system also achieved the $1.34 \times$ and $2.22 \times$ higher energy efficiency and throughput as compared to the state-ofarts. Yun-Chia Yu, Suraj Pn Reddy, Aryan Devrani, Anirudh Srinivasan, Saianudeep Reddy Nayini, Sohyeon Kim, Sung-Joon Jang, Sang-Seol Lee, Mingu Kang |
DAC | 6 |
| 2025 | Optimized Memory System Architecture for VESA VDC-M Decoder with Multi-Slice SupportabstractVideo compression plays a pivotal role in managing and transmitting large-scale display data, particularly given the growing demand for higher resolutions and improved video quality. This paper proposes an optimized memory system architecture for Video Electronics Standards Association (VESA) Display Compression-M (VDC-M) decoder, characterized by its substantial on-chip buffer requirements. We design and analyze three architectures categorized by optimization levels and management complexity. Our strategy focuses on enhancing line buffer access scheduling and minimizing reconstruction buffer, targeting prediction and multi-slice operation that are the major resource consumers in the decoder. By adjusting line delay and segmenting SRAM bank alongside reconstructed block forwarding, we achieve a 33.3% size reduction in the line buffer and 77.3% in the reconstruction buffer compared to Baseline VDC-M decoder. Synthesized using a 28 nm CMOS process, the proposed architecture achieve a 31.5% reduction in gate count of the decoder backend hardware, supporting real-time performance with up to 96.45 fps for 4K UHD resolution at 200 MHz operating frequency and a throughput of 4 pixels per cycle. Hannah Yang, Sohyeon Kim, Saeyeon Kim, Huijin Roh |
ISCAS | 2 |
| 2024 | Dynamic Resource Management in Reconfigurable SoC for Multi-Tenancy SupportabstractThis study introduces a partially reconfigurable system-on-chip (SoC) platform leveraging dynamic resource management facilitated by a dynamic reconfigurable control processor (DRCP). By addressing the inherent reconfiguration time overheads of reconfigurable SoCs, the study demonstrates performance improvements through a runtime resource management strategy. The introduced management scheme effectively reduces the frequency of reconfigurations, thus lessening the associated overheads and increasing the operational efficiency of the SoC platform, which is designed to support on-chip multi-tenancy. Utilizing DRCP for dedicated resource management, the proposed SoC platform exhibited substantial reductions in reconfiguration times. When the partially reconfigurable SoC platform employed four partial regions (PRs), the reconfiguration counts decreased by 37.6%. Furthermore, upon extending the PRs to eight, there was a notable reduction in reconfiguration counts, achieving a decrease of 47.0%. Sohyeon Kim, Injun Choi, Minkyu Je, Ji-Hoon Kim 0003 |
ISCAS | 1 |
| 2021 | ML-Based Humidity and Temperature Calibration System for Heterogeneous MOx Sensor Array in ppm-Level BTEX MonitoringabstractRecently, indoor air quality is an important issue for human health and high concentrations of toxic Volatile Organic Compounds (VOCs) gases such as BTEX (Benzene, Toluene, Ethylbenzene, and Xylene) are very harmful to our respiratory system and metabolism. To detect BTEX gases at indoors, Metal Oxide (MOx) sensors are widely used because of their low-cost and high sensitivity. MOx sensors are easily affected by temperature and humidity, hence it is difficult to detect BTEX gases accurately without additional calibration process. In this paper, we present the calibration system for heterogeneous MOx sensor array where machine learning (ML)-based techniques, Linear Regression (LR), Non-Linear Curve Fitting (NLCF), and Artificial Neural Network (ANN), are exploited to reduce the impact of temperature and humidity. For the performance evaluation, we have setup the gas concentration measurement system and recorded the sensor outputs from Temperature-Cycled Operation (TCO) responses of five heterogenous MOx sensors. The proposed calibration system with ANN-based calibration system shows the reduction of gas sensors variation due to temperature and humidity 73% on average, and presents maximum 92% reduction for benzene, 75% for toluene, 83% for ethylbenzene, and 91% for xylene gases, respectively. Hoyong Sung, Sohyeon Kim, Minkyu Je, Ji-Hoon Kim 0003 |
ISCAS | 3 |