This paper proposes a two-step down converter based on Pseudo 4-Phase Mutual Operation (P4MO) that uses inductors and coupled inductors to regulate output voltage (VOUT). By doubling the inductor current slew rate, the design reduces the intermediate capacitor (CINT) at VINTby nearly 50%. Additionally, conduction losses in the dual-output triple step-down (DOTS) input stage are reduced by approximately 30%. Moreover, a delayed feedback PWM technique further reduces the VINTripple by about 20%. An integrated soft turn-off circuit minimizes voltage variations at VOUTto less than 2 mV during phase shedding. Experimental results validate the design’s performance, showing a peak efficiency of 93.1%, undershoot of 106 mV with a recovery time of 1.9 μs for a load step transition from 1 A to 20 A, and a transient performance of 5.58 mV/A.

This paper proposes an isolated gate driver that incorporates an enhanced common-mode transient immunity (CMTI) technique to effectively suppress common-mode transient (CMT) noise. Additionally, the approach leverages the CMT noise to enable on-the-fly deadtime (DT) control at the transmitter. Experimental results demonstrate the DT jitter compensation circuit reduces high-frequency carrier (500 MHz) jitter by 10.6%, the efficiency is improved by 11.5%, and the CMTI is improved from 184 kV/μs to 208 kV/μs.

This paper proposes a two-phase hybrid buck-boost converter, which meets the criteria of USB PD 3.1, with an auxiliary inductor LAUX to achieve soft switching by the zero voltage switching (ZVS) technique at light loads. Besides, two interleaving phases can reduce the inductor current to half of that conventional design. Benefiting from a coupled inductor with a negative mutual inductance (M$_{\mathrm {L(AC)}}$becomes small to achieve low output voltage ripple due to large equivalent inductance Leq in a steady state. Based on the loading current, the phase shedding can change the number of driving phases for high efficiency. Moreover, a transient enhancement circuit is proposed to speed up transient response time. The proposed circuit achieves the maximum inductor current ripple reduction of 9.09% and the maximum P$_{\mathrm {AC\_loss}}$reduction of 17.36% at D=0.5. Experimental results show 96.1% peak efficiency. In the case of the load step 0.5A to 5A, the recovery time and undershoot are reduced to$10.7\mu $s and 133mV, respectively, and in the case of the load step 5A to 0.5A, the recovery time and overshoot are reduced to$9.4\mu $s and 147mV, respectively.

The series stacked (SS) FinFET structure is used in digital low dropout (DLDO) regulators to withstand high input voltages and implement dynamic voltage scaling (DVS) technique with minimum energy point (MEP) technique. Through an additional delay consideration in MEP, both energy reduction and performance of the Cortex M0 processor can achieve 34.5pJ/cycle at 0.5V. Maximum energy reduction is about 37.5% and the supplying voltage varies from 0.4V to 0.775V with a search time of 2.5μs for each voltage step. The proposed SS-DLDO has fast settling time and low output voltage ripple of 1.5μs and 5mV, respectively.