We propose switching activity factor-based effective current source model (SAFE) for aging-aware static timing analysis (STA), a new technique for estimating the timing performance of digital circuits. SAFE is based on the development of device-level variation-aware analytical timing models of stacked and multistage logic cells (commonly employed transistor topologies in a synthesized netlist of a random logic path), which drastically reduces the recharacterization efforts of the standard cells. The models developed are derived as a function of input transition time$(T_{R})$and load capacitance$(C_{L})$. The timing performance of a standard cell degrades with threshold voltage$(V_{\mathrm {th}})$degradation in a MOS device due to various aging mechanisms. SAFE, makes the entire STA process aging aware by updating its model coefficients with$V_{\mathrm {th}}$degradation caused by aging. It is achieved by proposing a method for estimating$V_{\mathrm {th}}$degradation under various stress conditions, including static, dynamic, and asymmetric, that applies to any process design kit (PDK). To consider asymmetric aging, we have developed a method to find effective switching activity factor$(\alpha _{\mathrm {eff}})$for N-stage stacked and N-stage parallel logic which is used to find the value of switching activity factor$(\alpha)$at intermediate nodes in pipelined logic circuits. Our simulations are performed in Mentor Graphics Eldo SPICE environment using STMicroelectronics 28 and 65-nm CMOS process. The proposed technique provides a high-simulation accuracy (2.5% average error) when compared with SPICE simulations. Finally, we achieved a ~98.14% reduction in the required number of simulations using SAFE when compared with a completely SPICE/Aging simulation-based approach.

A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage$(V_{\mathrm{ th}})$of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ($t$). A device-level approach for$V_{\mathrm{ th}}$degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of$t$. A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with$t$to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.

The concept of leveraging the transient negative capacitance (TNC) effect in a ferroelectric (FE) is a relatively new addition to the field of nanoelectronics. Until now, there has been no comparison of organic and oxide FE-based metal-FE-metal (MFM) devices in harnessing the TNC effect. As a result, we introduce an external resistor-MFM(R-MFM) series circuit to investigate the role of organic and oxide FEs in harnessing the TNC effect at low supply voltages. The multidomain Ginzburg-Landau-Khalatnikov theory is used to model the FE materials in a technology computer-aided design environment. We show that: (i) organic FE-based R-MFM series circuit can harness the TNC effect at just 1 V whereas an oxide FE-based R-MFM series circuit cannot; (ii) the coercivity of an organic FE is 77.39% lower than its counterpart, oxide FE; (iii) the remanent polarization of an organic MFM (1.2$\mu$C/cm2) is very close to the channel charge density of a CMOS transistor (1.6$\mu$C/cm2) making it helpful in addressing capacitance matching issues in NC transistor; (iv) an organic FE-based R-MFM series circuit dissipates 78.89% less energy than an oxide FE-based R-MFM series circuit; (v) the TNC effect and time are justified by its dependence on R. Finally, this article suggests that an organic FE-based MFM could be used as a gate stack of any transistor to achieve sub-60 mV/decade switching energy, making it ideal for ultra-low voltage NC transistors.

In this paper, the observation of transient negative capacitance signature (NCS) in an organic ferroelectric gate stack (OFEGS) at minimum supply voltage (Vs) of ±0.5 V is investigated employing a well-calibrated Ginzburg-Landau-Khalatnikov (GLK) model in the environment of Sentaurus technology computer-aided design (STCAD). We observe an 88.62 to 94.76 % reduction in the average coercive voltage (Vc) of the proposed OFEGS, which is still a significant challenge for the conventional ferroelectric (FE) lead zirconate titanate. We study the resistor-OFEGS (RCofe) series network behaviors in response to a bipolar and unipolar triangular signal. Our findings prove that the presence of NCS is directly correlated with the FE polarization (FEP) switching and not because of any extrinsic defects in the system. The various impacts of Vs, GLK parameters, R, dipole switching resistivity (Rofe) variations on the NCS response are investigated. The proposed OFEGS can harness the NCS effect at ±0.5 V with minimum energy dissipation of 4.81 × 10-16J, a challenge for the oxide FE-based gate stacks. Calibrating R to the maximum limit, we can capture the S-shaped ideal Landau path where the NCS is maximum with a small deviation of about ±0.006 V at zero FEP. Finally, an OFEGS based Landau transistor is implemented, providing a minimum subthreshold swing (SSmin) of 38.21 mV/decade, which is 36.32 % lesser than the fundamental SSminlimitation of 60 mV/decade. Therefore, the proposed OFEGS with a minimum Vs and remanent polarization (Pr=3D 1.244 μC/cm2) could be used as a gate stack for designing sub-60 mV/decade transistor technology.