Multibit (MB) quantization allows high resolution Delta-Sigma modulators (DSMs) with low oversampling ratio (OSR). Furthermore, it allows higher maximum stable amplitude (MSA), achieves reduced jitter sensitivity, and relaxes the dynamic requirements on the DSM loop-filter (LF). However, MB quantization adds a dominant source of non-linearity due to element mismatch in the MB digital-to-analog converter (DAC) which often dominates the performance. State of the art (SoA) presents many calibration techniques, though digital power and area consumption can be high and calibration time be significant. In this paper we target a calibration-free DAC based on dual quantization and propose to employ a Multistage noise SHaping (MASH) Digital-DSM (DDSM) to avoid architectural compromises between the main DSM LF and the DDSM DAC. The implementation trade-offs are illustrated, and stability constraints in both the main LF and the DDSM are addressed. An exemplary implementation is derived and simulated, and the results shall lay the foundation for future circuit implementations of MASH DDSM to realize MB DSM with intrinsically high linearity.

Active RC-Integrators are one of the main building blocks of continuous-time Delta-Sigma-Modulators (CTDSMs). The DC gain and gain-bandwidth product (GBW) of their Operational Ampifiers (OAs) play an important role in the modulator stability and performance in terms of signal-to-quantization-noise ratio (SQNR) as well as spurious-free dynamic range (SFDR). Negative-R assisted integrators have been introduced to reduce the CTDSMs sensitivity to OA non-idealities, where the negative-R has shown linearity improvements in low-power CTDSMs for relatively narrow bandwidth applications. However, the negative-R concept has not been widely applied for wideband applications. Wide-band CTDSMs in particular are more sensitive to the non-idealities of the OA GBW and especially in the associated phase-shift compared to their narrow-band counterparts. This paper provides insight into the effect of negative-R assistance on the GBW of the OA, where it is shown, that the phase-shift of the integrator due to finite GBW is not reduced by the negative-R assistance, and still remains an issue to be considered in the design of a wide-band CTDSMs.

This work presents a 600MS/s 10-bit single-channel asynchronous successive-approximation-register (SAR) analog-to-digital converter (ADC) using a highly linear unit via-based delta-length capacitive digital-to-analog converter (C-DAC). The plain and regular segmented C-DAC structure is presented in detail, which provides close to 13-bit static matching with an area of only 1160 μm2. A Flash ADC is employed to pre-load some MSBs for improved conversion speed while also efficiently utilizing DAC segmentation, which is practically necessary in delta-length-based C-DACs. This ADC architecture can easily be extended to a time-interleaved SAR to fully take advantage of the fast Flash conversion. The ADC was fabricated in a 22nm FDSOI technology and achieves a SNDR of 51.37dB at 600MS/s with near Nyquist input while consuming 3.04mW from a 0.85V supply, which leads to a Walden FoM of 16.74fJ/conversion-step.

As wideband Delta-Sigma-Modulators (DSMs) are restricted in oversampling ratio (OSR), and low OSR reduces the benefit of higher order loop filters, the increase of the internal resolution is an obvious way to achieve high signal-to-quantization-noise ratio (SQNR). State-of-the-art implementations restrict the internal resolution to mostly 4-6 bits, as efficient QTZs with higher resolution add excessive delay into the DSM. Multi-step or time-interleaved-quantizer (TI-QTZs) are an effective way to enhance resolution at high sampling rate, but the resulting latency in excess of one clock cycle usually prohibits their usage in DSMs. This paper proposes a new architecture to employ high resolution multi-step QTZs, such as TI SAR or pipeline ADCs. In the proposed architecture, an excess loop delay (ELD) of several clock cycles in the LSBs is purposefully allowed. While the MSBs are conventionally ELD-compensated, the LSBs are not. The resulting error is corrected in the digital domain. It is shown that matching requirements are relaxed by first-order shaping. The idea is also applicable to a Leslie-Singh and noise-coupling architecture, which are compared to the proposed architecture in an extensive system-level analysis and simulation. Depending on the target application, an advantageous design recommendation can be given based on the presented results depending on OSR, internal bitwidth and expected analog-digital matching.

Excess loop delay (ELD) in high speed continuoustime (CT) Delta-Sigma-Modulators (DSMs) imposes design challenges and limits the use of high resolution, e.g. successiveapproximation-register (SAR) based internal quantizers, as usual compensation techniques like the use of a direct path around the quantizer come with increased swings and reduced maximum stable amplitude (MSA). In this paper, two bitwise ELD compensation approaches applicable to cascade-of-integrators with distributed feedback (CIFB) loop filters are proposed, which alleviate this problem for SAR and other multi-step quantizers by sequentially feeding bits into the feedback loop when they are available (MSB first, LSB last). Loop-filter equivalence for such bitwise ELD compensation is analytically derived. System-level simulations using Matlab & Simulink for exemplary 4-bit 2nd, 3rd and 4th-order modulators show 40% reduction of the last integrator output swing compared to the conventional direct path compensation. This potentially allows to avoid the swing, quantizer scaling and noise trade-offs due to ELD in state of the art designs.

The performance of a 0-X MASH DSM is primarily defined by the DSM noise-shaping and the inter-stage gain (ISG). Due to system specification like modulator order and OSR, the DSM noise shaping is limited. All further performance in the 0-X MASH modulator is achieved by setting a large ISG, which amplifies the residue signal before it is processed by the fine stage DSM. This paper presents an analysis of the factors influencing the ISG and proposes measures, which can be used to maximize it. Most importantly, it is shown, that the CIFB DSM architecture is preferred, since the wideband residue overloads the CIFF architecture with its peaking OOB STF much earlier, thus CIFB results in more ISG and less internal swings. The presented analysis can be used as a guideline for achieving optimum performance in a 0-X MASH DSM and yielding the maximum SQNR.

The performance of Continuous Time Delta-Sigma Modulators (CT-AEMs) is limited by clock jitter in the outermost feedback DAC. As one solution, FIR-DACs have been introduced to improve the modulators jitter robustness. In literature, those FIR-DACs have been described with equal coefficients for all taps. This paper investigates the effect of using non-equal symmetric taps on the modulators performance. A comparison between the two FIR filters (equal and non-equal symmetric taps) regarding jitter immunity, sensitivity to coefficient mismatch, complexity of the filters and the required compensation filter are presented. Furthermore, the effect of the FIR filters on the modulators dynamic requirements and its STF are discussed. The paper shows that symmetric non-equal coefficients outperform the equal coefficients configuration in all aspects without sacrificing hardware complexity, resulting in an extension of the modulator's jitter immunity limit and reduction of power consumption.

This paper analyzes the effect of signal transfer function (STF) peaking in continuous-time (CT) Delta-Sigma- Modulators (DSMs) arising from excess loop delay (ELD) and its compensation. Starting from a generic model, the origin of different contributors to STF peaking are revised, namely noise transfer function (NTF) peaking due to aggressive noise shaping, instability from uncompensated delay as well as forward loop filter zeros in cascade-of-integrators with distributed feedforward (CIFF) modulators. The shift of forward loop filter zeros as a result of ELD compensation is shown intuitively for a 3rd order example, while system-level simulations of various 2nd, 3rd and 4th order CT single-loop modulators confirm increased STF peaking in the above stated scenarios.