This paper presents an energy-efficient residue amplification for low-power high-speed pipelined SAR ADC, whose residue amplifier is assisted by a dynamic negative capacitance (NC) circuit at the virtual ground. This dynamic NC for the residue amplifier increases the feedback factor while maintaining the closed-loop signal gain, thereby relaxing the requirements of the residue amplifier such as unity-gain bandwidth and open-loop gain, which subsequently leads to a power reduction of the residue amplifier. The proposed dynamic NC addresses the issues associated with static counterparts while maintaining small gain error, increased effective bandwidth, and high energy efficiency. Fabricated in a 28-nm CMOS process, the prototype 11-bit pipelined SAR ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 58 dB and a spurious-free dynamic range (SFDR) of 77.9 dB with Nyquist input at a sampling rate of 360-MS/s, while consuming only 3.9 mW from a 0.95 V supply. This corresponds to a Walden figure-of-merit (FoM) of 16.7 fJ/conv.-step, making this work competitive among the state-of-the-art ADCs with similar speed and resolution.

This article presents a continuous-time (CT) linear-exponential incremental ADC (IADC) that achieves 15-bit resolution at 250kHz bandwidth with 40 cycles for one conversion. It is based on an energy-efficient CT linear-exponential IADC, which alleviates the requirements of the power-hungry input buffer and loop filter. The proposed IADC employs a coarse 9-bit first-order IADC followed by a fine 8-bit cyclic ADC. The first-order IADC performs the coarse conversion by linearly accumulating input signals, resulting in a small thermal noise penalty. The residual quantization noise is exponentially reduced by the cyclic ADC, significantly shortening the conversion cycle. The cyclic ADC achieves the required accuracy by reconfiguring the loop filter of the coarse IADC and effectively compensating for the excessive loop delay. The prototype CT IADC is fabricated in a 65-nm CMOS process. With a 20MHz clock, it achieves 88.6-dB SNDR, 89.3-dB SNR, 90.1-dB DR, and 103.1-dB SFDR at a conversion rate of 500 kS/s. It consumes only 2.4 mW from a 1.2 V supply. It achieves the Schreier FoM (SNDR) of 168.8dB.

This paper proposes a pipeline ADC consisting of a first stage SAR ADC and a second stage Flash ADC. This ADC has a 10-bit resolution at 0.9 V power supply voltage and operates at 400 MS/s. The first stage SAR ADC is 6bit resolution, operates in an asynchronous type, and calibrates the offset of the internal comparator before normal operation of the ADC. The second stage Flash ADC outputs 5 bit digital outputs, and a sub-ranging scheme is used to reduce the number of pre-amplifier required. This prototype ADC is manufactured using 28nm CMOS process and consumes 4.55mW power at 400MS/s operation at 0.9V supply voltage, and the chip area is 0.011mm2. The SNDR of 50.5 dB at input frequency 1 MHz, the SNDR of 45.2 dB at 100 MHz input was obtained.