High-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) typically require bit weight calibration. The bit weight self-calibration technique is extensively used for its fully digital operation and low circuit complexity. Nonetheless, the comparator offset easily saturates the calibration circuit and leads to large bit weight errors in high-resolution scenarios, which needs to be cancelled in the analog domain. Moreover, the calibration needs to be repeated many times to reduce the circuit noise during calibration. These increase circuit complexity and calibration time. In this paper, a 16-bit SAR ADC with dual-segmental bit weight self-calibration is presented. The proposed calibration scheme increases the offset tolerance and suppresses the circuit noise during calibration. Therefore, precise analog-domain offset cancellation is not required, and the calibration time can be reduced. With these merits, the 16-bit SAR prototype designed in a 180-nm CMOS process achieves 16-bit linearity in only 370 clock cycles for calibration. The offset tolerance also increases to 7.5 mV. The extra analog circuit overhead for calibration reduces from high-resolution analog offset compensation circuits to only a comparator with a much-relaxed precision requirement, preserving the simple and scaling-friendly nature of SAR ADCs. With a sampling capacitance of 7 pF, the SAR ADC converts the signal at 4 MS/s with a peak signal-to-noise-and-distortion-ratio (SNDR) and a peak spurious-free dynamic range (SFDR) of 87.5 dB and 102 dBc, respectively. It consumes 10.1 mW from both 1.8-V and 3-V supplies and achieves a Schreier-figure-of-merit (FoM) of 170.5 dB at 4 MS/s.

This paper presents an efficient 8-MS/s 16-bit successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed symmetric complementary switching (SCS) and split passive reference segmentation (SPRS). Conventionally, improving the SAR ADC speed compromises the signal-to-noise-and-distortion ratio (SNDR) and energy efficiency due to the high precision requirement and the sequential bit-cycling. In this design, the proposed SCS scheme reduces the parasitic capacitance in the sampling path and the settling error of the capacitive digital-to-analog converter (CDAC) with low SNDR and hardware penalties. In addition, to reduce reference ripples, active reference buffers generally consume high power while the passive methods may degrade the SNDR or occupy large areas. To efficiently reduce reference settling errors, an area-efficient SPRS is developed, which suppresses the reference settling error through the split reference segmentation. The prototype chip is fabricated in a 180-nm CMOS process and occupies an area of 0.57 mm2. Measurements show the ADC achieves a peak SNDR of 89.2 dB at 8 MS/s with a 9.5-mW power consumption. The Schreier-figure-of-merit (FoM) is 175.4 dB.

This article presents a new asynchronous least-significant-bit (LSB) averaging technique to improve the signal-to-noise ratio (SNR) of high-precision successive-approximation-register (SAR) analog-to-digital converters (ADCs) with high power efficiency. After normal conversion, a linear searching is performed to coarsely reduce the conversion error asynchronously. Subsequently, the comparator performs a complementary number of comparisons with unchanged residue voltages to further reduce the error. Compared to traditional statistical noise reduction methods, the proposed method is insensitive to process, voltage, and temperature (PVT) variations since it does not require knowledge of the noise distribution. Additionally, it only slightly reduces the signal bandwidth as only 10 extra cycles are required. Therefore, the proposed method is suitable for low-noise, high-resolution SAR ADCs with MS/s speed. The proposed technique is implemented on a 16-bit SAR ADC in a 180-nm CMOS process. Running at 1 MS/s with the proposed technique, the measured signal-to-noise-and-distortion ratio (SNDR) is improved from 91.8 dBFS to 95.1 dBFS, and the dynamic range (DR) is improved from 93.8 dB to 98.1 dB. With power increased by 6.2% and period increased by 11%, this technique leads to a 2.59 dB Schreier figure-of-merit (FoM$_{\mathrm {SNDR}}$) and a 3.59 dB FoMDR improvement. The ADC consumes 7.1 mW and achieves a 173.6-dB FoMSNDR and a 176.6-dB FoMDR, respectively.

High-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) commonly need to calibrate their bit weights. Due to the nonidealities of the calibration circuits, the calibrated bit weights carry errors. This error could propagate during the calibration procedure. Due to the high precision requirement of these ADCs, such residue error commonly becomes the signal-to-noise-and-distortion ratio (SNDR) bottleneck of the overall ADC. This article presents an analysis of the residue error from bit weight self-calibration methods of high-resolution SAR ADCs. The major sources contributing to this error and the error reduction methods are quantitively analyzed. A statistical analysis of the noise-induced random error is developed. Our statistical model finds that the noise-induced random error follows the chi-square distribution. In practice, this random error is commonly reduced by repetitively measuring and averaging the calibrated bit weights. Our statistical model quantifies this bit weight error and leads to a clearer understanding of the error mechanism and design trade-offs. Following our chi-square model, the SNDR degradation due to the circuit noise during the calibration can be easily estimated without going through the time-consuming traditional transistor-level design and simulation process. The required repetition time can also be calculated. The bit-weight error models derived in this article are verified with measurement on a 16-bit SAR ADC design in a 180-nm CMOS process. Results from our model match both simulations and measurements well.

This article presents a timing-skew-free time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC). By implementing an architecture with a single sample-and-hold (S/H) network, this design eliminates the need for a costly timing-skew calibration. Additionally, compared to architectures that utilize multiple S/H networks, it offers hardware and power savings. As a result, the proposed design is efficient in terms of energy and area, making it suitable for applications that require multiple ADC channels. A prototype ADC is designed and fabricated in a 28-nm CMOS process. The TI SAR ADC, running at 1.4 GS/s, achieves a signal-to-noise-and-distortion ratio (SNDR) and spurious free dynamic range (SFDR) of 48.1 and 58.4 dB with a Nyquist input, respectively. It dissipates 24 mW, leading to a Walden figure-of-merit (FoM) of 82.4 fJ/conv.-step. The chip occupies an active area of 0.06 mm2.

This article presents an injection-locked clock multiplier (ILCM) using a digitally controlled frequency-tracking loop (FTL) with an integral two-step switched-capacitor (SC) digital-to-analog converter (DAC). Conventionally, the DAC resolution needs to be increased for low noise at the cost of degraded monotonicity due to device mismatch. To overcome this tradeoff, the proposed DAC utilizes the SC technique to achieve fine steps. With only two capacitors involved in charge transfer, the DAC is inherently monotonic, avoiding the boundary-crossing issue and the mismatch calibration. A control-voltage-tracking loop (CVTL) further suppresses the quantization noise by balancing the up and down step sizes and helps achieve a 16-bit-level voltage step. The FTL is sub-sampling and utilizes a bang-bang phase detector (BBPD). Locking at 700 MHz, the ILCM achieves a 0.9-ps integrated jitter, a -125-dBc/Hz phase noise at a 1-MHz offset, and a small jitter variation of 2.67% under different supply voltages and temperatures. With FTL, the spur is around -56 dBc from the prototype fabricated in a 180-nm CMOS process. The chip occupies a core area of 0.054 mm2 and consumes$689~\mu $W from a 1.8-V supply, achieving an FoM of -242.5 dB.

To increase the energy extraction capability and thus improve the power efficiency, it is critical to reduce the energy loss of interface circuit in the energy harvesting (EH) system. The synchronized multiple bias-flip (SMBF) control has been proposed and proved to be highly effective to increase the output power in piezoelectric EH systems. However, many existing designs based on bias-flip suffer from the limitations in real application as the external control or supply are required. Moreover, the control algorithm is often only suitable for a designated transducer and inductor. In this paper, an integrated piezoelectric EH interface circuit with synchronized triple bias-flip (S3BF) has been proposed to flip the voltage across the parasitic capacitor of piezoelectric transducer during the zero-crossing. Meanwhile, the adaptive control of the flipping signal has also been adopted to meet the requirement of different configurations of transducers and inductors. The proposed interface circuit has been designed in 0.18-μm CMOS technology. Without any external control circuit or power supply, it can achieve cold start-up when the external inductances vary from 33 μH to 500 μH. When the external inductance is 50 μH, the simulated flip efficiency is 87.2 %, and the maximum output power is 17.4 μW, which is 3.4 times of the full-bridge rectifier.