This paper presents a power-efficient autonomous current adaptation input driver (ACAID) for analog-to-digital converters (ADCs), which employs floating-gate transistors to provide reconfigurability. The proposed ACAID autonomously increases the supply current at the onset of the tracking phase, achieving a high slew rate. As the driver output voltage gradually follows the input signal in the RC-settling or hold phase, the supply current successively diminishes back to the original low quiescent level. The required sensing and actuating circuits for current adaptation are inherent components in the adopted capacitive feedback topology. A prototype version of the proposed ACAID has been designed and fabricated in a$0.35\um$CMOS process, along with integrated charge programming circuits and a 10-bit successive approximation register ADC. With$0.5\pF$sampling capacitors loading the driver, the proposed ACAID achieves$-70.1\dB$total harmonic distortion (THD) with a$100\kHz$input signal with$2.8\Vpp$amplitude. When connected to an on-chip ADC with a$200\kHz$sampling rate, the measured effective number of bits (ENoB) near the Nyquist rate is 9.1. The proposed ACAID saves more power as the input frequency increases or when the portion of the tracking period reduces. The prototyped driver circuit can save$49.5\%$power consumption when the input frequency is$100\kHz$with a$10\%$duty cycle for tracking. The power-saving ratio can be up to$76.2\%$when the sampling rate increases to$1\MHz$.

A cold start-up circuit for thermoelectric energy harvesting systems is presented in this paper. The proposed cold start-up circuit shares the energy harvesting inductor and load capacitor with the main boost converter, so no extra off-chip components are required, resulting in a small form factor. The start-up circuit comprises a stacked ring oscillator, a pair of low-voltage charge pumps, a low-power voltage detector, a reset switch, and two power switches. A prototyped chip for concept proving is designed and fabricated in a$0.18\ \mu \mathrm{m}$CMOS process. The measured waveforms demonstrate that the prototyped cold start-up chip can boost an input voltage of 300mV up to 1V within 950ms when the loading capacitance is$0.1\ \mu \mathrm{F}$.

In this paper, a four-channel floating-gate-based analog front-end (AFE) integrated circuit is presented. Each channel consists of a low noise amplifier (LNA), two operational-transconductance-amplifier-capacitor (OTA-C) biquadratic filters, and two buffer amplifiers. Floating-gate transistors deployed in a two-dimensional array are utilized to facilitate circuit reconfigurability and to achieve better power efficiency. Floatinggate programming circuities are also designed on-chip. Furthermore, a serial-peripheral interface (SPI) circuit with floating-gate transistors as non-volatile memories is adopted as the circuit parameter storage as well as the control interface during floatinggate programming. A prototype chip is designed and fabricated in a 0.35 μm CMOS process, occupying an area of 13.62 mm2. The measured current consumption of a single sensing front-end channel is only 76 nA with the noise efficiency factor of 5.82. The measured output signal magnitude is 564.3 mVppwith 1% total harmonic distortion.