In recent times, approximate computing has emerged as a promising technique to achieve significant power and energy benefits in computational systems. It is widely employed in fault-tolerant computationally intensive applications that require large arithmetic blocks. Applications such as image processing and machine learning often invoke the Multiply-Accumulate (MAC) unit for convolution operations. This paper proposes a novel architecture for an (unsigned × unsigned) approximate rounding and truncation based MAC unit named ART-MAC. It replaces the accurate multiplier architecture with an approximate multiplier proposed along with this work, thus improving the overall Quality of Results (QoR). The proposed design consumes 35.35% less power and showcases a significant speedup of 1.23 times when compared to the conventional MAC unit. On an average, the ART-MAC consumes 7.44% lesser on-chip area and showcases 13.49% lesser power-delay-product (PDP) compared to existing state-of-the-art designs.

Approximate Computing aims at achieving better performance at a marginal loss of accuracy in error-resilient applications. Several approximate arithmetic circuits have been proposed in the past which use carry prediction schemes, block-based approaches and genetic algorithms. However, these architectures are usually non power-aware and often incur large area overhead with the introduction of re-configurability. This work explores a new facet of approximation, which involves using the Unified Power Format (UPF) model to introduce approximation on additions. We call this methodology AxLEAP. Further, we validate the proposed methodology on a new approximate adder, which we term as AxL-Add. AxL-Add has a simple and re-configurable design with a marginal area overhead of 1.69% over accurate adder. After extensive evaluation, we show that our methodology is up to 67% better in terms of power consumption while providing near accurate results at the end application.

In recent times, approximate computing has found significant use in applications that can tolerate partially inaccurate results. This tolerance can be exploited to design simpler hardware aimed at getting area and energy benefits. In this work, we propose a novel technique to multiply two unsigned binary numbers through a Segmentation based Approximate Multiplier (SAM). The proposed design reduces the size of the Partial Products Matrix (PPM) in the order of n × (2n — 1) to a Reduced Partial Product Matrix (R-PPM) of the order 4 × 2n. Additionally, it also eliminates the extra hardware required for compression and rearrangement of partial products. μ-SAM, an optimized version of our basic design is also proposed along with this work. μ-SAM further minimizes the on-chip area and power consumption of the basic design. The basic design consumes 32.43% lesser on-chip area when compared to the conventional Wallace tree multiplier [1] and produces results that are 89.1% more accurate when compared to other existing state-of-the-art designs such as TOSAM [2], LETAM [3], and DQ4:2C4 [4].