This paper proposes a novel redundancy-based approach to drastically relax the matching requirements of CDACs and employing a cost-effective digital calibration method to improve linearity. The proposed architecture features a 3-segment CDAC with two redundant bits, which effectively reduces the overall DAC area and improves the DAC’s linearity. A 15-bit version of the DAC has been implemented in TSMC 0.18 μm technology, occupying a total area of 0.010 mm2. The design is validated through simulations in Cadence Spectre and calibration in MATLAB, resulting in worst-case integral nonlinearity (INL) and differential nonlinearity (DNL) of less than 0.5 LSB and 1 LSB, respectively, across 200 Monte-Carlo iterations.

This article presents a systematic approach to generate layouts for two devices, with an arbitrary integer ratio of device sizes, that cancels up to at least third-order gradient effects. A new analysis leads to mathematical constraints on 1-D layouts that meet the required integer ratio and cancel second-order gradients. From those layouts, we apply reflection and rotation symmetries to generate 2-D layouts that cancel higher-order gradients. We demonstrate our proposed methodology on current sense transistors interspersed in active power transistors. Legato electrothermal simulation show our proposed approach, respectively, improves worst-case matching accuracy about a factor of 9.9 and 7.15 when compared to a common centroid (CC) and interdigitated (ID) pattern in the presence of gradients effects. Furthermore, we discuss evaluation metrics that can be used to select one of multiple gradient canceling layouts for any fixed rectangular grid and device application.

This paper describes a low-cost technique for extracting parameters of interest for test boards used in multisite automatic test equipment (ATE). In the proposed approach, physical elements and nets on the PCB are represented as a graph with nodes and edges. Graph traversal algorithms are then used to extract data about the connections between specific components on each test site. This approach automates the previously slow and manual process of generating the topology files necessary to extract board parameters. The proposed method is implemented on a multisite test board, and results are presented.

Multisite (parallel) testing is becoming more widely used in analog and mixed-signal testing to increase throughput and meet high customer demand. However, site-to-site variations are inevitable due to the complexities involved in massive multisite test board design. Sites with pronounced systematic errors (issue sites) lead to measurements not reflecting the true performance of the device under test (DUT), causing potential yield loss and test escapes. Traditional mechanical repair of such sites is expensive, time-consuming, and labor-intensive. Polynomial transformation methods have been successfully explored to calibrate measurements at issue test sites. However, its rigid application could lead to overfitting or underfitting without foreknowledge of the nature and level of induced errors. This paper presents an optimal order polynomial transformation method that is flexible and self-adaptive. It uses a predefined error metric to find the optimal-order of the transformation polynomial and provides optimal calibration coefficients. Simulations and real test data are used to evaluate the effectiveness of the proposed method. Further validation is also provided by comparing the die measurements of issue sites after calibration against a more accurate reference.

The multisite test hardware is built with imperfect elements. Hence, like all measuring instruments, measurement errors are induced by test sites. These errors (random and systematic) are usually insignificant to guarantee test quality. However, as the number of test sites on the multisite tester increases (to further increase throughput), the induced systematic errors for some test sites become pronounced. The measurements of some test sites no longer reflect the true performance of the device under test (DUT), and the likelihood of yield loss or potential test escapes is increased. While multisite test hardware troubleshooting and correction can be difficult, time-consuming, and expensive, it is much easier to calibrate the measurements of issue sites (test sites with unacceptable systematic variations). This paper proposes a least-squares method for systematic hardware error identification and calibration. This method uses linear regression to compare the distribution of measurements at each test site to that of a reference (true and expected) distribution as a means to identify systematic errors and calibrate them. This approach provides a practical black box technique to mitigate test hardware systematic variations and further guarantee test quality. MATLAB® experiments indicate our approach outperforms existing methods in terms of accuracy. Application of the method to real test data confirms the effectiveness and robustness of the method without compromising test quality.

Multisite testing has become a proven method to reduce test time and costs for integrated circuits (IC). However, the technique suffers from site-to-site variations, especially when a large number of test sites are involved. It becomes imperative to identify issue sites that exhibit unacceptable variations to prevent yield loss or incorrect passing of faulty devices. By correctly identifying the true probability distribution of tested specifications, identification of issue sites becomes easier. We introduce an ordinal optimization-based algorithm to select the right sites to estimate the true distribution in situations where it is difficult or impossible to find the true distribution for tested specifications. Using both simulation and real-world ATE test data, we demonstrate that this approach yields good results.

Multisite testing significantly increases throughput by testing multiple chips simultaneously. When implemented on a large scale (massive multisite), the complex signal routing involved, interference, and coupling on the test hardware (amongst other issues) often affect test sites differently, introducing variations in site measurements. We hypothesize in this paper that each test site’s measurement can be modeled as a weak nonlinear function of the true chip measurement with systematic errors. We propose an algorithm to detect these systematic errors and calibrate them. This approach provides a practical black box technique to mitigate test hardware variations while investigating the fundamental root causes. The proposed method is verified with simulation and real test data.