Coverage guided dynamic verification is a widely used verification technique for RTL designs described using domain-specific languages for hardware and representing in some intermediate representations. Although the embedding of fuzz testing promote the abilities of coverage guided dynamic verification, there are lack of efficiently metric feedbacks utilization. In this paper, we proposed MMFuzz, a novel fuzzing tool enhanced by metric feedbacks. The proposed method utilze metric feedbacks efficiently in two aspects: seeds selection and mutators selection. The experimental results on several practical designs show that our method is able to achieve up to 1.0x improvements over the state-of-the-art RTL fuzzing tool with the same times of mutation.

With the successful application of hardware agile design methodology, it has become a big challenge to optimize the design in novelly defined intermediate representations (IR), such as FIRRTL. However, there is little work focusing on this challenge, or the optimization tasks are left to logic synthesizers by translating IRs into designs in hardware description languages (HDL).

Dynamic verification method is still the most easily accessible and thus heavily used verification approach for System-on-Chip (SoC) designs. Assertions are widely used in dynamic verification for functional coverage analysis. At present, how to generate tests to effectively cover assertions defined over internal signals is still a challenge for dynamic verification. In this paper, we propose a novel test generation method to accelerate assertion coverage using surrogate logic model. A surrogate logic model is used to represent an approximate relationship between an internal signal and related input signals, which is derived from simulation results by using machine learning technology. With surrogate logic model, we transfer the test generation for assertion coverage problem to a random sampling problem and solve it by the state-of-the-art sampling techniques. Experimental results on diverse benchmarks demonstrate that the proposed method could accelerate assertions coverage in two aspects, one is covering an assertion as quick as possible and the other is covering an assertion more times in a given period.

Recently, hardware agile design methods have been developed to improve the design productivity. However, the mod-eling methods hinder further design productivity improvements. In this paper, we propose and implement a microprocessor agile design method using feature oriented programming technology to improve design productivity. In this method, designs could be uniquely partitioned and constructed incrementally to explore various functional design features flexibly and efficiently. The key techniques to improve design productivity are flexible modeling extension and on-the-fly feature composing mechanisms. The evaluations on RISC- V and OR1200 CPU pipelines show the effectiveness of the proposed method on duplicate codes reduction and flexible feature composing while avoiding design resource overheads.

With the ending of Moore's Law and Dennard scaling, modern System-on-a-Chip (SoC) trends to incorporate a large and growing number of specialized modules for specific applications. Verification is vital to the RTL design and faces new challenges due to the growing design complexities. In this paper, we proposed a symbolic simulation enhanced coverage- directed dynamic verification technique for RTL designs. We proposed novel Full Multiplexer Toggle Coverage (FMTC) to trace and provide feedback to the verification process. The proposed method is a hybrid between symbolic simulation and mutation based fuzz testing that offsets the disadvantages of both. The achievement of high coverage is obtained by interleaved symbolic simulation and fuzz testing passes. The symbolic simulation pass is used to generate tests that direct the testing to untouched corners. While the mutation based fuzz testing pass is used to leverage test generation tasks and to enable the method to deal with large scale designs. The empirical evaluation of the method shows promising results on archiving high coverage for practical designs.