This work presents a half-bridge gallium nitride (GaN) buck converter using an adaptive charge sharing bootstrap (ACSB) technique to stabilize the bootstrap capacitor voltage. The conventional bootstrap technique relies on preset calculation to decide the bootstrap capacitance. However, the PCB parasitic capacitance and Qgvariations compromise the results. Moreover, the fixed bootstrap capacitance limits the practicality in monolithic gate drivers and only few GaN transistors with certain gate charge (Qg) range can be used. The proposed ACSB improves the conduction loss and avoids the gate overstress in GaN devices. In addition, the charge sharing technique requires merely a small on-chip bootstrap capacitor, which eliminates the bulk volume of the off-chip capacitor. The prototype is simulated in TSMC T18HVG2 process. Simulation results show that when Qgranges from 115 pC to 585 pC, the bootstrap voltage steadily maintains at 4.7 V. The overshoot and undershoot are 16.2 mV and 19.6 mV, respectively when the load current transits between 2A and 500 mA. The peak power efficiency of 93.2 % is obtained.

A digitally controlled dual-mode buck converter using low quiescent current is proposed in this work. In particular, the proposed dual pulse-skipping mode adopts a pulse-skipping adaptive on-time (PSAOT) mode for heavy load; and a pulse-skipping asynchronous mode (PSAM) for light and ultra-light loads to achieve a 100,000X wide load range for the Long-range (LoRa) application. Specifically, the pulse-skipping mode selector adopts a digital logic circuit to realize the 180nA low quiescent current. In addition, a low-power dynamic comparator with an adjustable offset is used to accelerate the transient response. The proposed converter is fabricated in a TSMC 350 nm CMOS process and results in an output voltage of 3.3 V from 5V to 4.2 V input voltage range. These results show that the overall system achieves 92.9 % peak eficiency at 8 mA output load and a figure of merit (FoM) of 2.29.

This paper proposes a dual-mode digital-control buck converter, which provides a 100,000X wide load range for internet of things. The proposed dual pulse-skipping modes include a pulse-skipping adaptive on-time (PSAOT) mode in the heavy load and a pulse-skipping asynchronous mode (PSAM) in the light load. The controller and mode selector are implemented in digital circuits that consume only 40.5 nA quiescent current. The proposed load detector does not require any extra current sensor. Not only the switching loss but also the quiescent power dissipation is minimized. A low-power dynamic comparator with adjustable offset is proposed to suppress the overshoot in transient responses. The proposed converter is designed in TSMC 350 nm CMOS process. Simulation results show that the converter provides a 3.3V output voltage from a 3.8V to 5V input voltage in a load range of $1 \mu \mathrm{A}$ to 100 mA. A 94.7% peak efficiency at 20 mA output loading and a Figure of merit (FoM) of 0.48 are achieved.

This paper proposes a battery management system, including a fast battery charger, battery aging diagnosis, and charge estimation and balancing. The charger adopts a single-inductor single-input dual-output architecture to achieve charge balancing among battery cells. Interleaved pulse charging is proposed to reduce the charging time and slow down the aging process of batteries as well. This method also significantly suppresses the variations of the temperature of battery cells and is beneficial to the implementation of charge balancing. An artificial neural network is proposed to detect the state of health (SOH) of battery cells and improve the accuracy of the state of charge (SOC) estimation. The prototype is implemented in TSMC 0.35-$\mu \text{m}$process and TensorFlow tools are used. Measurement results show that the interleaved pulse charging reduces 30% variation of the battery temperature and saves 24% charging time when charging four battery cells concurrently. A mean absolute error of SOC estimation of 0.35% is achieved in this work.

A battery management system with aging detection based on artificial neural network (ANN) for the state of charge (SOC) balancing is proposed in this paper. The charger adopts a single-inductor multiple-output architecture to achieve charge balancing among different battery cells. In constant current mode, the pulse charging is utilized to improve the charging speed and slow down the aging rate. Moreover, an ANN is proposed to detect the state of health (SOH) of the battery cells and improve the accuracy of the SOC estimation. TSMC 0.35-pm process and TensorFlow are used for simulations. A 94% power efficiency of the charger is achieved. The active area of this design is 1.5 × 1.5 mm2. Experimental results show that 0.32% root-mean square errors for the SOC estimation is obtained.