This paper presents an inductor-first tri-path (IFTP) buck converter suitable for USB power delivery adapter to charge 1-2 cell battery. The proposed topology adopts the inductor-first strategy and the tri-path strategy of one inductor path and two capacitor paths to extend the output voltage conversion range, realize the continuous input current, eliminate the input EMI noise, and reduce the inductor current. In addition, a phase-interleaved symmetric inductor-first tri-path (PIS-IFTP) buck converter is proposed to alleviate the inrush current in the flying capacitor under extreme duty cycle of IFTP converter, while further reducing inductor current ripple. Two experimental prototypes for 9 V input to 3-8.4 V ouput have been developed, demonstrating excellent ability of IFTP and PIS-IFTP topologies to reduce inductor current and achieve continuous input current over the whole duty cycle and load range. The experimental results validate that the prototypes provide a wide voltage conversion range of 1/3-1 and a maximum output current of 1.8 A. The peak efficiency of IFTP is 93% at$V_{OUT} \,\, =6.6$V, while the peak efficiency of PIS-IFTP is 94.5% at$V_{OUT} \,\, =3.3$V.

This paper proposes a loop-free self-balancing technique of flying capacitor for three-level buck converter. The pro-posed converter utilizes two balancing switches in self-balancing circuit, which can adaptively change the series and parallel structure of flying capacitors at different working phases. In two operating modes of duty cycle less than 0.5 and greater than 0.5, the converter can stabilize the flying capacitor voltages at$V_{IN}\mathbf{/2}$without any balancing feedback calibration loops. This three-level converter prototype is designed in$\mathbf{0.18\mu \mathrm{m}}$BCD process. When input voltage is set to 6V, the converter can provide a 0.4-5.6V wide output voltage range and automatically calibrate flying capacitor voltage to 3V under different conversion ratios and load currents. Simulation results show that the maximum output voltage ripple and inductor current ripple are 2.5mV and 174mA respectively when conversion ratio is equal to 0.25 or 0.75.

This paper presents a novel single-stage dual-output wireless power transfer system with an adaptive global power control. The power of freewheeling mode mentioned in the traditional reconfigurable regulating rectifier is used as another output, which achieves high light-load power conversion efficiency (PCE) of the receiver. The voltage of one channel is regulated by a local constant on-time control, while another channel is regulated by the adaptive global power control. In this way, all of the received power is almost transmitted to the output. This proposed wireless power transfer system is designed in a 0.18 μrn BCD process, and regulates two outputs voltage of 4 V each. The maximum output power is 840 m W with a peak PCE of 93.1%. Compared with the local voltage-regulation, the light-load efficiency improvement reached 17.5%.

This paper presents a current-injection-based balancing circuit for three-level DC-DC converter. Compared with the method of adjusting duty cycle to achieve flying capacitor balance, the proposed circuit avoids the unbalanced problem without affecting the frequency. In order to adjust the flying capacitor voltage adaptively, a digital controlled feedback loop with 9-bit counter is adopted. The three-level DC-DC converter is designed in a 0.18μ m BCD process, and the input voltage range is 3-6V. Simulation results show that the proposed converter has a good performance of flying capacitor balance with a peak efficiency of 96.8%. The output voltage ripple and inductor current ripple can reach 0.15% and 1.06% of the output voltage and load current, respectively.

This paper presents a high-voltage inverting converter implemented by reconfiguring a buck DC-DC regulator. The negative output voltage is generated from a positive input voltage by exchanging the output and ground on a buck converter. In this way, the complexity of circuit design is greatly reduced. The converter adopts constant on-time control with on-chip ripple compensation and output DC offset elimination techniques to achieve fast transient response and highly accurate output voltage, which also allows the use of output capacitor with low equivalent series resistance (RESR). In addition, an internal bootstrap circuit for high-side driver is proposed in place of conventional LDO structure to improve the efficiency. The converter is fabricated in 0.18-$\mu$m BCD process. The input voltage is in the range from 5V to 48V. The measurement results show that the transient response is about 220$\mu$s and the overshoot or undershoot voltage is less than 190mV when the load transient between 100mA and 500mA for switching frequency of 300kHz, input voltage of 24V and output voltage of-12V.

A fully-integrated relaxation oscillator with a typical frequency of 1.37 MHz is proposed. Neither comparators nor the reference voltage is required in the proposed oscillator. A constant with temperature (CWT) current source has been utilized to achieve good temperature stability. Moreover, a conventional comparator has been replaced with a voltage controlled delay element (VCDE) to avoid the comparator offset effect. Furthermore, frequency variation against supply voltage has been eliminated by matching bias voltages of the current starved delay element (CSDE) in the ramp generator and VCDE. The proposed relaxation oscillator is implemented with 0.25 μm BCD process. The measured results show that the frequency variation against supply voltage is within ±0.6%.