Chiplet-based (2.5-D and 3-D) multidie packages typically feature numerous die-to-die interconnects using micro-bump connections and possibly through-silicon vias or interposer wires, which are prone to manufacturing defects, such as shorts and opens, in both hard and weak (resistive) variants. Traditional I-ATPG methods only cover hard defects and scale with the logarithm of the number of interconnects. Despite being considered efficient, they cover shorts between all interconnects, including those for which shorts are unrealistic given their relative layout positions. This article proposes E2I-TEST, which covers all hard and weak variants of open defects and of only the shorts and coupling defects between physically adjacent interconnects for both 3-D and 2.5-D chips, while preventing aliasing during fault diagnosis. This article further improves E2I-TEST to prevent ground bounce, avoiding undesired voltage fluctuations during test mode. While the number of interconnects is expected to rise significantly, E2I-TEST offers a high-quality interconnect test, while maintaining a constant number of test patterns.

The success of chiplet-based design critically depends on standards, especially those for die-to-die interconnects. Universal Chiplet Interconnect Express (UCIe) is such a standard, showing promising potential in its field. Among other things, UCIe standardizes the micro-bump map. It incorporates several spare interconnects able to "repair" defective interconnects. We outline a very efficient, aliasing-free test generation method for all hard and weak short and open manufacturing defects on die-to-die interconnects that uses just 16 test patterns, irrespective of the number of interconnects. We also propose to improve repairability of the UCIe interconnects through reorganizations of the micro-bump map that eliminate the risk for non-repairable (‘catastrophic’) defects and minimizes the usage of spare interconnects. The micro-bump map reorganizations are not backwards compatible and hence, since UCIe is still in its early stages of actual usage, it would be best to incorporate this improvement in the standard as soon as possible.

Quantum computers aim at solving computationally hard tasks exponentially faster than classical computers. Among the different platforms that are candidate for the realization of a large-scale fault-tolerant quantum computer, Si spin qubits are one of the most promising, due to their manufacturability and long coherence times. Spin qubits operate in a3He/4He dilution refrigerator, featuring extremely low operating temperatures (tens of millikelvin) as well as long cool-down times. Testing at cryogenic temperature is extremely expensive, not only due to the required equipment and the long cool-down time, but also due to the limited number of packaged devices that can be tested in a single cool-down cycle. Our research aims at defining a parametric test routine for high-volume room-temperature screening of MOS Si spin qubit arrays, to select good candidates for cryogenic temperature testing. In this paper we measure Single Electron Transistors (SETs), that represent the overall quality of the array, and report experimental results to investigate which transistor metrics are more relevant for the device screening, comparing room-temperature data at 295K to 4K and 40mK data.

Chiplet-based multi-die packages (a.k.a. 2.5D- and 3D-ICs) implement large amounts of inter-die interconnects with micro-bumps. To achieve uniform heights, these micro-bumps are typically placed in large rectangular or hexagonal arrays. These interconnects are subject to manufacturing defects. Traditional interconnect automatic test pattern generation (I-ATPG) methods, such as the True/Complement Algorithm [1], focus on hard open and short defects with test pattern count 2 × ⌈log2(k)⌉ for k interconnects. However, the traditional I-ATPG methods indiscriminately cover short defects between all pairs of interconnects, including those for which shorts are unrealistic given their relative layout positions. In this paper we propose an effective and efficient interconnect test (E2ITEST). The proposed method improves the test effectiveness by covering both hard and weak variants of open and short defects. It improves the test efficiency by considering only shorts between adjacent interconnects. Because of this, it requires 8 × ⌈log2(4)⌉ = 16 test patterns, thereby decoupling it from the dependency on k, which is large already today and only expected to grow.

Electron-spin qubits in silicon are one of the most promising platforms for implementing large-scale quantum computing. In this platform, a qubit, i.e., the basic unit of quantum information, is associated with the spin of a single electron confined in a region of silicon called a quantum dot. Electron-spin qubit devices must be operated at the cryogenic temperature of 40mK in a 3He/4He dilution refrigerator. This requirement results in long cool-down (“soak”) times and increased costs, which slow down the technology development. Our research aims at developing a high-volume, room-temperature screening technique to assess quantum dots variability and select suitable candidates for mK measurements. In this paper, we present transistor measurement data of quantum dots across a 300mm wafer at temperatures ranging from 300K down to 225K. We analyze the statistical distributions of transistor metrics to detect outliers across temperatures, and hence to prevent wasting measurement time and resources at mK on known bad devices. From the collected data, we conclude that among the metrics analyzed, the threshold voltage appears to be the preferred metric for an effective pre-screening of silicon quantum dots.

Chiplet-based multi-die packages implement large numbers of inter-die interconnect bundles clustered in large micro-bump islands. These micro-bumps can be subject to manufacturing defects. The most common defect types are shorts and opens. Traditional interconnect automatic test pattern generation (I-ATPG) algorithms detect, for a given collection of interconnects, all shorts between any pair of interconnects, all open interconnects, and exclude any aliasing, independent from the interconnects’ layout positions. Exploiting knowledge of their relative layout positions, we derive a new, improved I-ATPG algorithm. For a user-defined and scalable definition of realistic shorts, the new I-ATPG approach (1) increases the defect coverage significantly (in an example case, between 18% and 67%) by including realistic inter-bundle shorts between micro-bumps from adjacent bundles, and (2) reduces the overall test pattern count (and hence, the resulting test time) by 33% by providing test patterns for realistic shorts only.

Cell-aware test (CAT) offers a high-quality test that explicitly targets potential cell-internal open and short defects. CAT requires to characterize library cells to determine which cell patterns can detect which cell-internal defects. Characterization is performed only once per library, but in today's implementations [1], [2] it is nevertheless a very time-consuming task, since it performs analog simulation on every library cell c, for every potential defect d, and with every cell pattern p. However, after the lengthy simulation, invariably a majority of the defect/pattern tuples (d, p) turns out to be undetectable. Often, an undetectable tuple (d, p) can be identified only on the basis of the topology of the cell's transistors netlist. We refer to this as logical undetectability. This paper presents an efficient algorithm that performs a structural analysis of library cells to identify all logically undetectable tuples (d, p), which then can be excluded from the time-consuming analog simulation. As our structural analysis is a lot faster than the analog simulation, their combination delivers significant speed-ups; for 476 standard cells from Cadence's GPDK045 library [3], the algorithm identified 47% of logically undetectable tuples.