This paper presents a power-efficient fourth-order, 50-MHz active-RC filter with high dynamic range (DR). Unlike conventional Tow-Thomas biquads, the proposed design employs a passive integrator as the second pole to reduce power consumption, enhance noise performance, and facilitate frequency compensation. The active integrator features a two-stage operational transconductance amplifier (OTA) with a push-pull output, ensuring linearity and reducing the OTA’s gain requirements. Fabricated in standard 0.18-μm CMOS technology, the proposed filter achieves an in-band (IB) input third-order intercept point (IIP3) of +29.9 dBm at 30 MHz and an input-referred IB integrated noise of 163.8 μVRMS, while consuming 5.4 mW for a 50-MHz bandwidth.

A 50 MHz bandwidth (BW) transimpedance ampli-fier (TIA) is designed for 5G Sub-6GHz SAW-less current-mode receivers (RX). It's based on an operational transconductance amplifier (OTA). To tolerate blockers, the TIA must exhibit excellent in-band (IB) and out-of-band (OOB) linearity, which in turn requires OTAs with high BW and gain. Traditional two-stage OTAs struggle to achieve this under low power consumption (PC), so this paper employs a three-stage OTA. A pseudo-differential structure without the tail current source is used to accommodate low supply voltages (Vdd). Differential-mode (DM) stability relies on feedforward (FF) compensation within the OTA and zero compensation in the feedback network. Common mode (CM) is stabilized by five different common mode rejection (CMR) techniques. The circuit is designed and simulated in a 40 nm low power (LP) CMOS technology with a Vdd of 1.2V. The post-layout simulation results show that when IM3 is set to 30 MHz, the TIA's IB and OOB IIP3 reach 31.6 dBm and 50.6 dBm, respectively. The minimum input-referred noise (IRN) is 5.14$\mathbf{nV}/\sqrt{Hz}$. The corresponding FoM value is as high as 186.3 dBJ-1, exceeding all previous designs. The chip consumes 10.4 mW of power and occupies only 0.016mm2.

The operational amplifier is a key building block in analog systems. However, the design process of the operational amplifier is time consuming and heavily depends on engineers’ experiences. This article presents OPAMP-Generator, an analog operational amplifier generator, which automates the full design flow from user-defined specifications to GDSII layout without human intervention. OPAMP-Generator includes behavioral-level topology optimization, efficient sizing algorithm based on the classical$ {g_{m}/I_{d}}$design methodology, and automated layout generation. The behavioral-level description of the opamp is represented by the directed acyclic graph (DAG) and a customized variational graph autoencoder is proposed to embed the discrete graph representation into a low-dimensional continuous space. The topology of the opamp can thus be optimized in the latent space, which greatly improves the optimization efficiency. The sizing algorithm based on${g_{m}/I_{d}}$methodology can guarantee the quality of transistor-level circuit implementation. The constraints of the layouts can be naturally derived from the topology level, which facilities the automatic generation of layouts. Experimental results demonstrate that our proposed method can efficiently synthesize operational amplifiers with competitive performances compared to manual designs.

Operational amplifier is a key building block in analog circuits. However, the design process of the operational amplifier is complex and time-consuming, as there are no practical automation tools available in the industry. This paper presents a new topology optimization method for operational amplifiers. The behavioral description of the operational amplifier is described using a directed acyclic graph (DAG), which is then transformed into a low-dimensional embedding in continuous space using a variational graph autoencoder. Topology search is performed in the continuous embedding space using stochastic optimization methods, such as Bayesian Optimization. The yield search results are then transformed back to operational amplifier topologies using a graph decoder. The proposed method is also equipped with a surrogate model for performance prediction. Experimental results show that the proposed approach can achieve significant speedup over the genetic searching algorithms. The produced three-stage operational amplifiers offer competitive performance compared to manual designs.

A wideband LNTA based on cascode inverters is presented, suitable for 5G Sub-6GHz applications. Cascode technique improves the bandwidth, reverse isolation and output impedance. Noise canceling(NC) technology and the new derivative superposition method are adopted to achieve better noise and linearity, respectively. Intrinsic second-order input impedance and off-chip L-type and T-type matching networks are utilized to increase the S11 bandwidth. The use of MOSFETs with different threshold voltages(Vth) simplifies the bias circuit. The first stage of the LNTA is a shunt-shunt feedback LNA, where the feedback resistance Rfaffects the four key performances of gain, bandwidth, noise and linearity. By adjusting the value of Rf, the LNTA can work either in low noise(NF mode) or high linearity(IIP3 mode). The LNTA is designed under the TSMC40nmLP process, and the post-layout simulation shows that the noise figure(NF) can be as low as 1. 52dB under the NF mode. The IIP3 and PldB can reach 10. 58dBm and -1.46dBm respectively under the IIP3 mode. The overall power consumption is only 15. 49mW. The chip core has no inductors and capacitors, making its area only 0.0026mm2.

Operational amplifier is a basic component for analog circuit design. The compensation network of an operational amplifier is crucial to improve the stability of the operational amplifier. In this paper, we present an automated compensation scheme design approach for operational amplifiers. We map the behavioral-level description of the operational amplifier to an acyclic graph and transfer the compensation design problem into a topology optimization problem. A feature mapping method is proposed to encode the graph and a bi-level Bayesian optimization approach is proposed to efficiently solve the topology optimization problem. Experimental results show that our proposed method can obtain competitive three-stage operational amplifiers compared to manual designs.

This paper presents a 4th-order active-RC low-pass filter (LPF) with tunable cut-off frequency (20-50 MHz). To achieve high in-band linearity performance, a three-stage opamp with an operational transconductance amplifier (OTA) output stage is adopted. The first two stages of the opamp only introduce about 45° phase shift using Miller-feedforward hybrid compensation scheme, which guarantees the stability of the filter. The designed opamp can achieve 47 dB gain and 1.4 GHz gain-bandwidth products (GBW) for the filter with 50 MHz cut-off frequency. The post-layout simulation results show that the filter consumes 5.7 mW from 1.1 V supply voltage. The in-band integrated input-referred noise (IRN) is 473 μVrms. The filter achieves 29.8 dBm IIP3 at 30 MHz. Due to the high in-band linearity performance, 153.4 dB · J-1of figure-of-merit is achieved in this design.