This effort describes a Python-based open-source tool to synthesize a mixed-signal reconfigurable IC fabric, known as large-scale Field Programmable Analog Array (FPAA) fabric. This tool starts from a high-level definition for an FPAA fabric to lower into gathered islands for each Computational Analog Blocks (CAB) and Computational Logic Blocks (CLB), and then extends the Ashes tool to first place and route each different island, and then place and route the full fabric. This tool integrates with the Ashes tool and expands both tools to enable synthesis of a configurable analog or mixed-signal reconfigurable fabric with other analog & mixed-signal standard cell components. The fabricated fabric could be targeted through the Ashes tool that integrates VPR into its place and route flow. The synthesis builds from recent innovations of programmable analog & mixed-signal standard cells that utilize Floating- Gate (FG) elements for their high-precision parameters. This effort demonstrates this synthesis entirely for 350nm standard cells with configurable chips that are synthesized to tapeout. These techniques generalize to other analog standard cell libraries (e.g. 130nm, 65nm, 16nm). A recent critical effort is the development of programmable analog & mixed-signal standard cells that utilize Floating-Gate (FG) elements for their high-precision parameters. These concepts, in-turn, enable the opportunity to both abstract higher levels of analog computation and enable large-scale analog synthesis.

Analog Hopfield networks perform continuous energy minimization, leading to efficient and near-optimal solutions to nonpolynomial (NP)-hard problems. However, practical implementations suffer from scaling and connectivity issues. A programmable and reconfigurable analog Hopfield network is presented that addresses these challenges through a reconfigurable Manhattan architecture with a high-precision 14-bit floating-gate (FG) compute-in-memory (CiM) fabric. The network is implemented on a field programmable analog array (FPAA) and experimentally tested on three different NP-hard problems with different scaling challenges: Weighted Max-Cut (high connectivity and weight precision), traveling salesman problem (TSP) (high connectivity and medium weight precision), and Boolean Satisfiability/3SAT (low connectivity and weight precision) where it solved each problem optimally in microseconds.

This work presents an experimentally measured, implemented, openly-available programmable analog standard cell library in Skywater’s 130nm CMOS process. Programmability enables standard-cell components, eliminating the need for large number of device geometries required in classic analog design. This effort presents the methodology in developing these analog standard cell library and integrating synthesis with these cells.

Physical computing techniques can efficiently solve combinatorial optimization problems and could outperform conventional digital techniques. This paper presents the first direct comparison of two physical quadratic optimization solvers: analog Hopfield and Ising networks. Both networks are built in a large scale Field Programmable Analog Array (FPAA) and two NP-hard problems (max-cut and associative memory) are solved over various initial conditions and graphs. The convergence time, energy, power, and peripheral circuitry of the two networks is then compared where it is found that the Hopfield network outperforms the Ising networks in these test cases.

Integrated circuit (IC) design for analog computing requires similar toolflows and synthesis as large-scale digital systems, in-turn necessitating a library of general-purpose analog cells. To this end, we present a programmable, floating-gate (FG)-based analog standard cell library in a commercially available 65 nm process that allows analog IC designers to use synthesis tools with an abstracted design mindset similar to large-scale digital design. We fabricate the test cells, which include filters with programmable corners, an analog classifier, and an arbitrary waveform generator (AWG); experimentally characterize FG programming; and experimentally demonstrate the performance of the standard cells. Overall, the standard cells achieve a similar or smaller footprint than previous approaches while leveraging the benefits of FG programming at smaller technology nodes.

This paper discusses physical computing for solving optimization problems using a Hopfield network built on a Field Programmable Analog Array (FPAA). A core Hopfield circuit is presented that uses a programmable Vector-Matrix-Multiply (VMM) and Transconductance Amplifier (TA). The circuit dynamics of the VMM and effects of mismatch are discussed. The analog Hopfield network is evaluated by inputting a graph to the network and solving the NP-hard max-cut problem. Experimental results show convergence time in the order of microseconds towards a optimal solution on a four and ten node graph.