As integrated circuit design continues to scale, three-dimensional integrated circuit (3D-IC) technology has emerged as a promising solution to extend Moore’s Law. Among various physical design stages, placement plays a pivotal role, directly influencing key power, performance, and area (PPA) metrics. In research that does not consider specific 3DIC process technologies, the state-of-the-art ePlace-3D introduces 3D electrostatic field density modeling, enabling nonlinear placement algorithms to truly address 3D placement problems. However, its complex flow results in low runtime efficiency. In this work, we propose LightPlace, a lightweight and effective 3D placement framework. This framework incorporates Virtual Macro Insertion approach and Macro Connection Reconstruction method, which streamline the macro placement phase and allocate space for subsequent standard cell placement. These innovations enhance runtime efficiency and optimize wirelength. Experimental results on the large-scale Modern Mixed-Size (MMS) benchmarks demonstrate that, LightPlace reduces total wirelength by an average of 10% and achieves up to 4× faster runtime compared to the runtime reported for ePlace-3D.

Graph partitioning is one of the fundamental problems in many graph-based applications and systems. It enables the division of a graph into smaller sub-graphs for subsequent parallel processing, reducing the processing latency of the graph. The critical path of a graph is the logical path with the longest delay from input to output. The processing time of the graph mainly depends on the delay incurred by the critical path, independent of other paths with small delays. Therefore, it can reduce the processing time of the graph by protecting the critical path of the graph from partition. However, existing approaches to graph partitioning only focus on metrics such as minimum cut and partition balance. As a result, the critical paths of graphs may be destroyed in the partitioning procedure. To address this problem, we present a critical path awareness approach, namely path-metis, to protect the critical paths and alleviate the processing latency after graph partitioning. In path-metis, two efficient strategies, including Slack and critical path fix strategies, are introduced. The Slack strategy, which incorporates critical path information into the weights of DAG, is used as pre-processing before traditional multi-level partitioning methods, like Metis. Then, for the generated partitioning scheme, the critical path fix strategy is proposed to further protect critical paths from being cut. We demonstrate the effectiveness of our approach on both real and synthetic datasets. From the experimental results, compared to Metis, our method improves critical path performance by 17.70%.

Deep learning services are extensively required and have powerful expected effects in a wide range of applications, such as auto-self driving, voice assistant and so on.Traditionally, deep learning services are mainly provided based on cloud computing, referred to as cloud intelligence services, where the deep learning model is deployed in the cloud, and endusers need to upload data through wireless and core network when requesting training and inference services. However, the cloud computing-based deep learning services have deficiencies in latency, privacy, etc. For example, the deep learning service users do not want their private data to leak, and the privacy problem is difficult to solve when the data is uploading to the cloud. With the widespread use of the Internet of Things (IoT) and the rapid development of mobile devices such as smartphones and IoT sensors, large amounts of data need to be used for a variety of real-time deep learning services, such as target recognition and voice recognition for smart cities, smart medical care, and the Internet of Vehicles (IoVs). With a certain network bandwidth, a large amount of data uploaded to the cloud will cause network congestion and greatly increase the response time. To meet the requirements of low latency, researchers have begun to consider the deployment of deep learning services in edges, i.e., edge intelligence service.In edge intelligence services, the computation capability and memory of processors (or devices) are different from a large. At the same time, the requirement of memory size of deep neural network (DNN) models is increasing, such as the memory usage for Alexnet and Resnet are 2.12G and 16.20G separately. Also, in DNN model design, the branches are becoming common, which brings the parallelism. Deploying deep learning models on multiple processors can support the large-scale DNN models and the parallel implementation of DNN model, where the computation of a deep learning model can be conducted in parallel is a possible solution to improve the efficiency of edge intelligence services. The key point in edge intelligence services is how to partition and assign the implementation of the DNN model.In this paper, we propose a novel latency-driven deep learning model placement method for efficient edge intelligence service. Model placement contains two procedures: model partition and sub-models assignment. In our method, we first convert a DNN model into an execution graph, which is a directed acyclic graph (DAG), and propose a novel latency-driven multilevel graph partition for the model. Then the partitioned submodels are heuristically assigned to available processors. To the best of our knowledge, it is the first work that proposes latency-driven graph partition algorithms for model placement. Extensive experiments on several commonly used DNN models and synthetic datasets show that our method can achieve the lowest execution latency with low complexity compared with other state-of-the-art model placement methods.

Deep learning services based on cloud computing have deficiencies in latency, privacy, etc. To meet the requirements of low latency, researchers have begun to consider the deployment of deep learning services in edges, i.e., edge intelligence service. Deploying deep learning models on multiple processors or devices so that the computation of a deep learning model can be conducted in parallel is a possible solution to improve the efficiency of edge intelligence services. In this article, we propose a novel latency-driven deep learning model placement method for efficient edge intelligence service. Model placement contains two procedures: model partition and sub-models assignment. In our method, we first convert the model into execution graphs and propose a novel latency-driven multilevel graph partition for the model. Then the partitioned sub-models are heuristically assigned to available processors. To the best of our knowledge, it is the first work that proposes latency-driven graph partition algorithms for model placement. Extensive experiments on several commonly used DNN (deep neural network) models and synthetic datasets show that our method can achieve the lowest execution latency with low complexity compared with other state-of-the-art model placement methods.

Functional verification of large scale circuit design is a basic problem in Very Large Scale Integrated (VLSI) design. With the increasing scale of the circuit, it is urgent to divide the whole large scale circuit into some smaller sub-circuits so as to perform parallel functional verification on multiple hardware processors. The partition problem of hardware-accelerated functional verification can be regarded as a graph partition problem. However, unlike the traditional graph partition requirements for minimum cutting, the hardware-accelerated functional verification partition needs to reduce the simulation depth and improve the parallelism of the simulation. Therefore, partition for hardware-accelerated functional verification is a problem combined with graph partitioning and schedule. While the traditional schedule algorithms have high complexity and cannot handle large scale Directied Acyclic Graph (DAG) scheduling. To tackle the parallelism, depth, and cut edge problem, we design a new method, called path-metis. Path-metis combines the scheduling idea, such as the critical path information and task priority of the DAG, into the traditional multilevel partitioning method. Our preliminary experiments on real circuits show the effectiveness of the method, and the simulation depth can be reduced by about 11.35% on average compared with metis only with 27.58% cut size increasing.