Designing and deploying real-time computing pipelines efficiently on modern embedded platforms is increasingly challenging due to the growing complexity of hardware architectures, often featuring multi-core processors, frequency scaling capabilities, heterogeneous cores for enhanced power efficiency, and hardware accelerators. OpenMP is a prominent tool for parallelizing applications on multi-core platforms and is gaining increasing adoption in the domain of real-time systems. However, providing sound performance guarantees on the timing behavior of complex parallel computations organized as graph structures on heterogeneous platforms, while achieving optimal or near-optimal energy efficiency, is all but trivial. This paper tackles this problem by proposing a methodology to deploy and analyze both traditional parallel real-time applications and OpenMP parallel applications, modeled as directed acyclic graphs (DAGs) and coexisting on the same heterogeneous platform. Specifically, the approach targets asymmetric multi-core platforms with frequency scaling capabilities, with the aim of minimizing energy consumption while guaranteeing end-to-end latency constraints via schedulability analysis. The proposed approach features an optimal solver based on a mixed-integer quadratic constrained programming formulation, and a computationally efficient heuristic to extract high-quality solutions with reduced solving time. The concept is experimentally validated using randomly generated sets of DAGs, optimized by the two techniques and deployed using an OpenMP-based DAG synthetic benchmark on Linux running on an embedded board. Results demonstrate that the methodology enables energy-efficient deployment of mixed traditional and OpenMP real-time DAG applications while preserving end-to-end latency guarantees.

Embedded computing systems are becoming increasingly complex. Modern system-on-chips come with heterogeneous designs that integrate diverse processing systems and a large variety of peripherals. When considering software with mixed and independent security and criticality levels, the heterogeneity of modern computing platforms poses considerable challenges in achieving strong isolation between execution domains. Tackling these challenges is even more difficult in platforms that integrate Field-Programmable Gate Array (FPGA) fabrics, which, due to their wide flexibility, introduce new security- and safety-related threats that can jeopardize isolation. As a matter of fact, if no proper countermeasures are in place, hardware accelerators (HAs) deployed on FPGA can be exploited to break the isolation capabilities implemented in a system by issuing dangerous bus transactions. This research proposes a design flow for heterogeneous platforms to strongly isolate bus transactions issued by HAs. The design flow is then specialized for the AMD Zynq UltraScale+ platform, leveraging the virtualizationrelated features of the Arm System Memory Management Unit (SMMU). The proposed solution jointly combines two new IPs for enforcing information transported by the AXI bus, a tool to verify the FPGA design, a principled configuration of the SMMU driver, and a secure boot flow. The proposal is evaluated with an industry-relevant use case related to embedded machine learning applied for the railway domain, in which isolation is established between two AMD Deep Learning Processor Units (DPU) and a set of FPGA HAs dedicated to a real-time critical application.

Graphics processing units (GPUs) are often employed to accelerate the inference of deep neural networks (DNNs) in cyber-physical systems to implement advanced perception and control functionalities. Frameworks for GPU-accelerated DNN inference typically aim at maximizing the processing throughput rather than focusing on providing a predictable timing behavior, which is crucial for time-sensitive cyber-physical systems. This work proposes a framework for GPU-accelerated inference of DNNs on GPU-based embedded platforms in multitasking scenarios, which provides enhanced timing predictability using a design-time optimization procedure of the DNN workload and a specialized method to schedule the GPU acceleration requests of the DNNs at runtime based on fixed-priority limitedpreemptive scheduling. Fine-grained control of the inference is achieved by splitting the DNNs into smaller chunks, which are then scheduled using a specialized real-time scheduling mechanism. Experimental results on commercial embedded platforms report significant improvements in terms of schedulability.

While preemptive Earliest-Deadline-First (EDF) has been studied extensively in real-time systems, there are only few results when considering tasks with dynamic self-suspension behavior scheduled under EDF. Furthermore, all schedulability tests that have been developed in this context are based on analyzing specific intervals, hindering the performance of the analytical tightness of the result. In this work, we develop a schedulability test for EDF, built on a dynamic interval extension. That is, whenever the analysis cannot derive a decision to conclude the schedulability test, we iteratively extend the analysis interval to include additional carry-in jobs into the analysis. This is achieved by specifying execution-exceedance requirement for infeasibility of the system, i.e., by specifying how much workload must be accumulated within a certain time interval to achieve a deadline miss. Our approach outperforms all previous analyses and is the first to surpass the schedulability guarantees that can be provided for Deadline-Monotonic (DM) scheduling for dynamic self-suspending tasks, hence achieving a milestone in the analysis of EDF scheduling.

Security threats are becoming an increasingly relevant concern in cyber–physical systems. Cyber attacks on these systems are not only common today but also increasingly sophisticated and constantly evolving. One way to secure the system against such threats is by using intrusion detection systems (IDSs) to detect suspicious or abnormal activities characteristic of potential attacks. State-of-the-art IDSs exploit both signature-based and anomaly-based strategies to detect network threats. However, existing solutions mainly focus on the analysis of statically defined features of the traffic flow, making them potentially less effective against new attacks that cannot be properly captured by analyzing such features. This paper presents an anomaly-based IDS approach that leverages unsupervised neural models to learn the expected network traffic, enabling the detection of unknown novel attacks (as well as previously-known ones). The proposed solution uses an autoencoder to reconstruct the received packets and detect malicious packets based on the reconstruction error. A careful optimization of the model architecture allowed improving detection accuracy while reducing detection time. The proposed solution has been implemented on a real embedded platform, showing that it can support modern high-performance communication interfaces, while significantly outperforming existing approaches in both detection accuracy, inference time, generalization capability, and robustness to poisoning (which is commonly ignored by state-of-the-art IDSs). Finally, a novel mechanism has been developed to explain the detection performed by the proposed IDS through an analysis of the reconstruction error.

With the recent advancements in computing power and energy efficiency, embedded system platforms have become capable of providing services that previously required compu-tational support from cloud infrastructures. Accordingly, the edge computing paradigm is becoming increasingly relevant, as it allows, among other advantages, to foster security and privacy preservation by processing data at its origin. On the other hand, these systems demand predictability across the IoT-edge-cloud continuum. Regardless of the communication link, real-time tasks at the edge send data on the network, employing one or more transmission queues. For a system designer, analyzing the timing behavior of a task becomes challenging when each task has to wait for a variable amount of time before sending a packet. This paper analyzes the transmission behavior of a network of nodes regarding the latency introduced when dealing with a communication interface. The proposed analysis provides necessary conditions under which the data traffic is guaranteed not to exceed the transmission queue limit, thus avoiding unbounded waiting times on task execution, while a response time analysis technique is provided to ensure the schedulability of periodic tasks executing in each node of the network. An experimental campaign was carried out to evaluate the schedulability performance obtained with different system configurations when the proposed analysis was applied.

Parallel execution and hardware acceleration involving specialized devices such as GPUs and FPGAs are becoming increasingly relevant in the domain of embedded systems. Communication between jobs dispatched on different cores and hardware accelerators is most often implemented using asynchronous events. Modeling the timing behavior of such systems requires to account for the delays incurred by each task due to the additional time spent waiting for events. This paper presents the event-driven delay-induced (EDD) task model to explicitly deal with complex computing workloads that incur such kinds of delays. The EDD task model generalizes several state-of-the-art models, such as the DAG task model and the segmented self-suspending task model, and is particularly suited to analyze parallel tasks that issue asynchronous hardware acceleration requests. Two analysis techniques for EDD tasks executing on single core platforms are first provided. We then extend those approaches to analyze parallel real-time tasks under partitioned multicore scheduling by means of a model transformation. Experimental results are presented to compare the two analysis techniques for EDD tasks proposed in the paper. Finally, we compare the analysis of partitioned parallel tasks modeled with EDD tasks against federated scheduling.