Continuous-flow microfluidic biochips (CFMBs) are advanced platforms that precisely manipulate fluids through micron-scale channels and have been widely applied in biomedical research and disease diagnostics. Their internal architecture typically employs multiplexer-based control logic, where control channels transmit input signals to flow valves to dynamically switch fluid paths and achieve precise control. However, the reuse and elimination operations of control channels introduce a large number of L-shaped structures. These structures are prone to channel deformation and, under high-frequency usage, can accelerate structural fatigue, thereby reducing the reliability of the control logic. In addition, improper control channel reuse may lead to signal conflicts and interference. To address these problems, we propose a control logic architecture design approach for CFMBs that simultaneously considers channel length and straightness. First, we propose a placement preprocessing strategy that integrates a heuristic initialization with a critical-path-first approach to improve the quality of the initial placement and ensure feasibility. Second, we design a placement algorithm based on discrete particle swarm optimization with a twin-swarm cooperative mechanism, which effectively explores better placement solutions through cooperative search between the two swarms and feedback from routing results. Finally, we propose a two-stage routing algorithm that integrates error recovery and reuse constraints. By incorporating straightened routing and reasonable reuse, this algorithm significantly reduces channel length and the number of bends while ensuring the correctness of the control logic. Experimental results demonstrate that the proposed approach enables reliable control of flow valves with fewer resources and effectively reduces signal propagation delay in control channels, significantly enhancing the overall performance and reliability of the control logic.

With the increasing integration level of flow-based microfluidics, fully programmable valve arrays (FPVAs) have emerged as the next generation of flow-based microfluidic devices. Microvalves in an FPVA are typically managed by a control logic, where valves are connected to a core input via control channels to receive control signals that guide their state switchings. When executing bioassays using an FPVA, however, some valves need to be switched synchronously at different time points, so that both fluid transportation and biochemical operations can be executed correctly. Consequently, the channel lengths from the core input to these valves must be equal, which poses a big challenge to the channel routing of the control logic. To solve this problem, we propose a deep reinforcement learning-based adaptive routing flow for the control logic of FPVAs. With the proposed routing flow, an efficient control-channel network can be automatically constructed to realize accurate control signal propagation. Meanwhile, timing skews among synchronized valves and the total length of control channels are minimized simultaneously, thus generating an optimized control logic with excellent timing performance. Furthermore, by introducing backups of identified critical valves and flexible routing of backup paths without restrictions on control valve locations, a novel fault-tolerant design method considering length matching is implemented to efficiently improve the reliability of the control logic. Simulation results on multiple benchmarks demonstrate that the proposed routing flow leads to control logics with accurate valve synchronization, low cost, and high reliability.

Routability has always been a significant challenge in Very Large Scale Integration (VLSI) design. To overcome the potential mismatch between the global routing results and the detailed routing requirements, track assignment is introduced to achieve an efficient routability estimation. Moreover, with the increasing scale of circuits, the intricate interconnections among the components on the chip lead to increased timing delay in signal transmission, thereby significantly impacting the performance and reliability of the circuit. Thus, to further improve the routability of the circuit, it is also critical to realize an accurate estimation of the timing delay within the track assignment stage. Existing heuristic track assignment algorithms, however, are prone to local optimality, and thus fail to provide accurate routability estimations. In this article, we propose an enhanced scalable parallel track assignment algorithm called SPTA 2.0 for VLSI design, employing a two-stage partition strategy and considering timing delay. First, the proposed algorithm achieves efficient assignment of all wires by considering the routing information from both the global and local nets. Second, the overlap cost, the blockage cost, and the wirelength cost can be minimized to significantly improve the routability. Third, a critical wire controlling strategy is proposed to optimize signal timing delays inside nets. Finally, a two-stage partition strategy and a panel-subpanel-level parallelism are designed to further reduce the runtime, improving the scalability of the proposed methodology. Experimental results on multiple benchmarks demonstrate that the proposed method provides better routability estimations, and leads to superior track assignment solutions compared with existing algorithms.

With the increasing integration level of flow-based microfluidics, fully programmable valve arrays (FPVAs) have emerged as the next generation of microfluidic devices. Mi-crovalves in an FPVA are typically managed by a control logic, where valves are connected to a core input via control channels to receive control signals that guide states switching. The critical valves that suffer from asynchronous actuation leading to chip malfunctions, however, need to be switched simultaneously in a specific bioassay. As a result, the channel lengths from the core input to these valves are required to be equal or similar, which poses a challenge to the channel routing of the control logic. To solve this problem, we propose a deep reinforcement learning-based adaptive routing flow for the control logic of FPVAs. With the proposed routing flow, an efficient control channel network can be automatically constructed to realize accurate control signals propagation. Meanwhile, the timing skews among synchronized valves and the total length of control channels can be minimized, thus generating an optimized control logic with excellent timing behavior. Simulation results on multiple benchmarks demonstrate the effectiveness of the proposed routing flow.

Fully Programmable Valve Array (FPVA) biochips have attracted much attention as a new generation of continuous-flow microfluidic platform for biochemical experiments automation. With the increasing density of microvalves in FPVA biochips, the control system for managing the open/close of these valves has become more and more complex. To improve the scalability of biochips and reduce the number of control pins, a highly efficient control system using multiplexer and boolean logic has been introduced in FPVA biochips. In the manufacturing and using of such systems, however, various faults such as channel blockage, channel leakage, and reliability issues caused by frequent valve switching can occur in the multiplexers. Accordingly, in this paper, we propose the first automated fault test method for the multiplexer of FPVA control systems. The proposed method includes the following key techniques: 1) an automated test pattern generation algorithm based on integer linear programming and 2) an automated fault test strategy based on image recognition technology. Experiment results on multiple benchmarks have shown that the proposed method can generate fewer test patterns, while achiving 100% fault coverage.

Fully programmable valve array (FPVA) biochips have emerged as a promising alternative for traditional application-specific microfluidic platforms thanks to their advantages in terms of flexibility and reconfigurability. By regularly deploying microvalves along vertical and horizontal flow channels, microfluidic modules with different sizes and shapes can be constructed dynamically on the chip, thereby enabling the automatic execution of various assay procedures in biology and biochemistry. The above advantages, however, result largely from the large-scale integration of valves as well as accurate control of their switchings, leading to very complicated control-logic design of such chips. In this article, we propose an reinforcement learning (RL)-based synthesis flow for the control-logic design of fully programmable valve array (FPVA) biochips, taking multichannel switching and control-cost minimization into consideration simultaneously. By employing a double deep$Q$-network (DDQN) and two Boolean-logic simplification techniques, control logics with both high-switching efficiency and low-fabrication cost can be constructed automatically. Furthermore, the solution space of multichannel-switching combinations is reduced to improve the search efficiency of the proposed method. Experimental results on multiple benchmarks demonstrate that the proposed synthesis flow leads to better-design solutions compared with the state-of-the-art techniques.