Testing advanced memories is essential for ensuring modern System-on-Chip quality. As transistor size continues to shrink, the probability of the occurrence of manufacturing defects increases, making conventional functional testing of SRAMs inadequate for achieving required Defect Parts per Million (DPPM). To address this issue, a novel structural testing approach using the Cell-Aware (CA) test methodology has been proposed in [1]. With this methodology, structural test patterns are obtained through an Automatic Test Pattern Generator (ATPG) by exploiting analog CA models (i.e., based on exhaustive analog simulations) for SRAM primary blocks. However, the generation of CA models through analog simulations is time-consuming and technology dependent. A methodology, namely TrUnDeL proposed in [2], is used to accelerate the CA model generation, combining a switch-level graph-based solution and analog simulations. In this work, we propose an adaptation of TrUnDeL to generate the CA models, using only the switch-level graph-based simulations. TrUnDeL CA models are then used by the ATPG to generate structural test patterns. Through a validation flow, we demonstrate that the aforementioned patterns, generated without running any analog simulations, achieve nearly the same fault coverage as the test patterns generated using exhaustive analog simulations on an SRAM case study. The time required to generate CA models is drastically reduced with TrUnDeL, from 1 hour to 15 seconds for the considered case study.

Modern integrated circuits such as System-On-Chip (SOC) require a large amount of memory. The integration density of these memories is based on the extreme miniaturization of the technological nodes. However, the miniaturization process contributes to an increase in the occurrence of physical defects. In order to verify the quality of memories, new test methods, based on structural testing, have been proposed recently. However, these methods rely on a digital test environment and require an accurate modeling of the memory. This work proposes a digital SRAM modeling compatible with digital simulation and test environments. The digital SRAM modeling presented in this paper is functionally equivalent to an analog SRAM model (i.e., memorization, Write and Read operations). The memorization capability of the model enables it to consider the data-background of the memory array during testing, facilitating the evaluation of complex test sequences, such as March algorithms, in covering structural fault models (i.e., Cell-Aware fault models).

Testing memory circuits is crucial for ensuring the quality and reliability of system-on-chip (SoC) designs, especially as shrinking technology nodes increase susceptibility to nanometer-scale defects. This article introduces an enhanced methodology for memory testing, leveraging the cell-aware (CA) test concept. Building on prior work for SRAM array testing (Xhafa et al., 2023), we extend the CA methodology to include periphery testing by generating, for the first time, CA models for each memory input–output (I/O) element, covering key components, such as address decoders, write drivers, and sense amplifiers. We present results from testing these periphery components using the CA methodology. Additionally, we compare existing SRAM testing techniques with our CA methodology for the decoder and I/O circuitry. To ensure a fair comparison, we selected minimal March tests designed to detect functional faults in peripheral circuits, aligning with the fault models targeted by our approach. A quantitative analysis of fault coverage demonstrates the effectiveness of our methodology compared to March algorithms, particularly in terms of test complexity.

The reduction in transistor size in modern Integrated Circuits (ICs) has led to an increase in manufacturing defects within standard cells, also known as intra-cell defects. Detecting these defects and localizing them through diagnosis is crucial for achieving a fast yield ramp-up and ensuring a low test escape rate. Traditional fault models, such as stuckat and transition, do not effectively represent intra-cell defects. To address this issue, the Cell-Aware (CA) methodology was introduced. However, this technique involves time-consuming analog SPICE simulations to characterize standard cells. This paper presents a methodology, called Transistor Undetectable Defect eLiminator (TrUnDeL), based on graph theory to speed up the CA model generation process. Our methodology identifies undetectable defects for each stimulus applied at the inputs of the cell, which are then excluded from the analog simulations. We applied TrUnDeL to two libraries from STMicroelectronics (P28 and C28) to identify the undetectable stimulus/defect pairs, so that analog simulations are performed only on the remaining pairs. As a result, the CA model generation process time is reduced by a factor of 3. Finally, we applied TrUnDeL to a SRAM bitcell case study and demonstrated that the obtained results are consistent with its existing CA model.

The shrinking of technology nodes has led to high-density memories containing large amounts of transistors which are prone to defects and reliability issues. Their test is generally based on the use of well-known March algorithms targeting Functional Fault Models (FFMs). This Ph.D. thesis aims to introduce a novel approach for advanced and emerging memory testing that relies on the Cell-Aware (CA) methodology to further improve the yield of System on Chips (SoCs).

The shrinking of technology nodes has led to high density memories containing large amounts of transistors which are prone to defects and reliability issues. Their test is generally based on the use of well-known March algorithms targeting Functional Fault Models (FFMs). This paper presents a novel approach for memory testing which relies on Cell-Aware (CA) methodology to further improve the yield of System on Chips (SoCs). Consequently, using CA methodology converts memory testing from functional to structural testing. In this work, the preliminary flow of the CA-based memory testing methodology is presented. The generation of the CA model for the SRAM bit cell has been demonstrated as a case study. The generated CA model and the structural representation of the memory are used by the ATPG to test the bit cell in the presence of short and open defects. The generated test patterns are able to detect both static and dynamic faults in the bit cell with a test coverage of 100%.