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Zhenguo Yin

dblp:297/3873 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 1 · 1 since 2021Theory of computation · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 50% Program verification · 50%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Compilers and program optimization
instruction encoding and decoding
0.512021
Automatic Generation and Validation of Instruction Encoders and Decoders · CAV (2) 2021
Electronic design automation › hardware verification and test
hardware verification
0.512021
Automatic Generation and Validation of Instruction Encoders and Decoders · CAV (2) 2021

Methods — techniques the papers use, named apart from their topics

coq proof synthesis · 1.0bijection-based generation · 1.0SMT solving · 1.0
YearPublicationVenuePosition
2021 Automatic Generation and Validation of Instruction Encoders and Decoders
abstract
Abstract Verification of instruction encoders and decoders is essential for formalizing manipulation of machine code. The existing approaches cannot guarantee the critical consistency property, i.e., that an encoder and its corresponding decoder are mutual inverses of each other. We observe that consistent encoder-decoder pairs can be automatically derived from bijections inherently embedded in instruction formats. Based on this observation, we develop a framework for writing specifications that capture these bijections, for automatically generating encoders and decoders from these specifications, and for formally validating the consistency and soundness of the generated encoders and decoders by synthesizing proofs in Coq and discharging verification conditions using SMT solvers. We apply this framework to a subset of X86-32 instructions to illustrate its effectiveness in these regards. We also demonstrate that the generated encoders and decoders have reasonable performance.
Xiangzhe Xu, Yuting Wang 0001, Zhenguo Yin
CAV (2)4