In modern DRAM design, IR-drop has emerged as a critical factor leading to operation failures, primarily due to reduced metal resources and increased supply current demands. Consequently, estimating and addressing IR-drop throughout the DRAM design process has become a crucial sign-off consideration. The proposed comprehensive methodology for the power delivery network (PDN) includes accurate and efficient estimation at two key stages: early in the design process (Early PDN) and during post-physical design sign-off validation (Iterative PDN). The Early PDN approach employs simplified modeling to achieve reasonable accuracy, serving as a guideline for the initial PDN design. Subsequently, the Iterative PDN method provides a fast yet detailed analysis of the entire DRAM, including the PDN, ensuring it is suitable for final sign-off. By applying this methodology, PDN behavior can be effectively predicted and optimized, ensuring robustness. This enhances the reliability and performance of DRAM designs.

This paper introduces a physical layout design methodology that produces DRC-clean, area-efficient, and programmable layouts of digital circuits in advanced DRAM processes. The proposed methodology automates the layout generation process to enhance design productivity, while still providing rich customization for efficient area and routing resource utilizations. Process-specific parameterized cells (PCells) are combined with process-independent place-and-route functions to automatically generate area-efficient and programmable layouts. Routing grids are optimized to enhance the area and routing efficiency. The proposed method reduced the design time of digital layouts by 80% compared to a manual design with high layout qualities, significantly enhancing the design productivity.